Tuple Encoding DMA Engine for Scratchpad Multi-Core Processors
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Solution Overview
Problem
Database servers executing on multi-core processors face inefficiencies in moving tabular data due to overhead from direct memory access (DMA) operations, with tabular data not being optimally formatted for DMA engines and limited local memory capacity leading to frequent interrupts and performance degradation.
Innovation Solution
A hardware-accelerated data movement system with multiple data movement engines and internal memories that perform data manipulation operations in-flight, using descriptors to optimize data movement and partitioning across core processors, and employing a copy ring for efficient data transfer and broadcast within the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA engine moves tabular data from main memory to local memory, then data movement is performed, but overhead from DMA operations and frequent interrupts deteriorate processor performance
Solution Approach 1:
The patent combines multiple data movement operations into a single DMA transfer by reorganizing tabular data into a concatenated format where multiple columns are merged into continuous memory structures. This eliminates the need for multiple separate DMA operations and interrupts, as the entire concatenated data structure can be transferred in one operation, thereby improving data movement efficiency while reducing processor overhead.
Solution Approach 2:
The patent performs preliminary data reorganization by concatenating columns into continuous memory structures before the DMA operation begins. This pre-processing step ensures that the data is already in the optimal format for efficient single-operation transfer, eliminating the need for complex runtime data manipulation and reducing the number of interrupts required during actual data movement.
2Ease of manufacture
If tabular data is stored in traditional row-major or column-major format, then data can be stored contiguously, but the data format is not optimal for DMA engine efficiency
Solution Approach 1:
The patent introduces a dynamic data representation where tabular data can be viewed and accessed in multiple formats (row-major, column-major, and concatenated column-major) depending on the operation requirements. The underlying storage structure is designed to support flexible interpretation, allowing the same physical memory layout to serve different logical access patterns, thereby optimizing DMA efficiency without sacrificing storage simplicity.
Solution Approach 2:
The patent changes the fundamental parameter of data organization from traditional row-major or standalone column-major formats to a concatenated column-major format where multiple columns are merged into continuous memory structures. This parameter change enables the DMA engine to transfer larger contiguous blocks of data in single operations, significantly improving DMA efficiency while maintaining straightforward memory allocation.
3Speed
If local memory size is small, then memory closer to core processor is available, but DMA engine must repeat data movement multiple times causing frequent interrupts
Solution Approach 1:
The patent segments the tabular data into multiple concatenated columns that together form a large continuous memory structure. This segmentation allows the data to be divided into manageable chunks that can be transferred in fewer, larger DMA operations rather than many small operations, thereby reducing interrupt frequency while maintaining fast data access through the local memory.
Solution Approach 2:
The patent enables continuous data movement by organizing data into concatenated column structures that can be transferred in unbroken sequences. This continuity eliminates gaps and interruptions in the DMA transfer process, allowing the data movement operation to proceed efficiently without frequent stops and restarts, thereby improving throughput while maintaining the speed advantage of local memory access.
Data Source
AI summary
Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine. Tabular data is efficiently copied between internal memories of the data movement system via a copy ring that is coupled to the internal memories of the data movement system and/or is coupled to a data movement engine. Also, a data movement engine internally broadcasts data to other data movement engines, which then transfer the data to respective core processors. Partitioning may also be performed by the hardware of the data movement system. Techniques are used to partition data "in flight". The data movement system also generates a column of row identifiers (RIDs). A row identifier is a number treated as identifying a row or element's position within a column. Row identifiers each identifying a row in column are also generated.