Turbo Code Interleaver Parameters for Lower Error Floors

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Solution Overview

Problem

Current convolutional turbo code (CTC) interleaving techniques in orthogonal frequency division multiple access (OFDMA) mode of IEEE 802.16 exhibit degraded performance with increasing block size and a distinct error floor above a block error rate of 10−4, failing to provide reliable information in noisy environments.

Innovation Solution

New parameters for the IEEE 802.16 convolutional turbo code interleaver are introduced, which improve performance with increasing block size and reduce the error floor, achieved by grouping and encoding information bits using specific values for N, P0, P1, and P2, and implementing an almost regular permutation scheme to enhance interleaving efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the prior art CTC interleaver parameters (P0, P1, P2, P3) are used, then the implementation is straightforward, but the code performance degrades with increasing block size and exhibits an error floor above a block error rate of 10^-4

Engineering Contradiction:
Improvecode performanceVSAvoidperformance across different block sizes
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies parameter changes by modifying the CTC interleaver parameters (P0, P1, P2, P3) to new values that are specifically designed to eliminate the error floor and improve performance with increasing block size. The new parameters are calculated based on the block size N, where P0 = 3N/4 + 1, P1 = N/4, P2 = N/4, and P3 = 3N/4, ensuring optimal performance across different block sizes while maintaining the same interleaving structure.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the prior art CTC interleaver parameters are used, then the system operates with existing standards, but the signal-to-noise ratio requirement is higher and block error rates are elevated

Engineering Contradiction:
Improveblock error rateVSAvoidsignal-to-noise ratio
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the interleaver parameters to achieve a block error rate of 10^-4 at a signal-to-noise ratio that is at least 0.5 dB smaller than prior art, and in some cases up to 1.3 dB smaller. This parameter optimization directly improves reliability while reducing the energy/signal-to-noise ratio requirement for achieving the same performance level.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7590044B2Method and apparatus for interleaving\within a communication system
Publication Date: 2009.09.15 GOOGLE TECHNOLOGY HOLDINGS LLC
  • US7590044B2 patent drawing
  • US7590044B2 patent drawing
  • US7590044B2 patent drawing

AI summary

A method and apparatus for interleaving within a communication system is provided herein. More particularly parameters for a convolutional turbo code interleaver are provided, and interleaving takes place utilizing the new parameters. The new parameters generate interleavers that have the correct turbo code behaviors of improving performance with increasing block size and an error floor well below a block error rate of 10−4. Furthermore, the parameters have no implementation impact. Interleaving in accordance with the preferred embodiment of the present invention can achieve a block error rate of 10−4 at a signal-to-noise ratio that is at least 0.5 dB, and in some cases up to 1.3 dB, smaller than that which can be achieved with the code using the existing parameters.