Three-Dimensional Turbo Code for Flash Drive Error Correction
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Solution Overview
Problem
Conventional approaches to error management in MLC flash memories, particularly in enterprise storage environments, are inefficient in achieving low uncorrectable bit error rates and long service life due to high write amplification and degradation over time.
Innovation Solution
A three-dimensional turbo code system is implemented, comprising primary, secondary, and tertiary error correction codes that provide orthogonal error correction across different dimensions, along with a journaling filing system to reduce write amplification and extend flash memory cell life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BCH error correction coding is used in MLC flash memory, then the implementation is simple and cost-effective, but the uncorrectable bit error rate is high and reliability is insufficient for enterprise storage
Solution Approach 1:
The patent segments the error correction task into multiple independent coding layers: a first ECC scheme (e.g., BCH) applied to first data portions, and a second ECC scheme (e.g., LDPC or Turbo) applied to second data portions. This segmentation allows each layer to be optimized independently, achieving high reliability through the stronger second ECC while keeping implementation complexity manageable through the simpler first ECC.
Solution Approach 2:
The patent introduces a hierarchical dimension to error correction by organizing data into multiple portions with different ECC protections. Instead of applying a single strong ECC to all data, the system creates a multi-layered protection structure where critical data portions receive enhanced protection, effectively adding a dimensional layer to the error correction approach.
2Reliability
If strong error correction coding is applied to all data portions, then reliability improves, but write amplification increases and flash memory life decreases
Solution Approach 1:
The patent applies different levels of error correction strength to different data portions based on their specific needs. Critical data portions receive stronger ECC protection while less critical portions use lighter protection. This local differentiation optimizes the balance between reliability and write amplification, extending flash memory life by avoiding unnecessary strong ECC on all data.
Solution Approach 2:
The system dynamically adjusts ECC parameters such as code rate, block size, and correction strength based on data characteristics, wear level, and error patterns. This allows the flash memory to maintain high reliability while adapting the ECC strength to minimize write amplification and extend device lifespan.
3Reliability
If multiple ECC schemes are implemented with different data portions, then reliability and error correction capability improve, but the complexity of the ECC management system increases
Solution Approach 1:
The patent clearly segments data into distinct portions (first data portions and second data portions) with dedicated ECC schemes for each. This segmentation simplifies management by creating well-defined boundaries and responsibilities for each ECC layer, making the system more manageable despite using multiple coding schemes.
Solution Approach 2:
The system performs preliminary classification and organization of data into appropriate portions before applying different ECC schemes. This preliminary action establishes a clear structure that simplifies subsequent ECC management and decoding operations, reducing the complexity burden of multiple ECC schemes.
4Reliability
If conventional single-layer ECC is used, then the storage structure is simple, but the ability to achieve low uncorrectable error rates over extended service life is insufficient
Solution Approach 1:
The patent adds a hierarchical dimension to error correction by implementing multi-layer ECC protection across different data portions. This dimensional approach enables the system to achieve low uncorrectable error rates over extended service life by providing progressive error correction capabilities that conventional single-layer ECC cannot deliver.
Solution Approach 2:
The system uses a composite error correction structure combining different ECC schemes (e.g., BCH + LDPC, or Turbo + BCH) in a hierarchical arrangement. This composite approach leverages the strengths of each individual ECC scheme to achieve superior long-term reliability that neither scheme could provide alone.
Data Source
AI summary
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.