Turbo Code Interleaver Circuit Using Lookup-Based Address Generation
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Solution Overview
Problem
Conventional circuits for implementing the 3GPP Turbo code interleaver are complex and inefficient, particularly in performing modulo operations, which leads to performance penalties and increased resource usage, especially for smaller block sizes.
Innovation Solution
A method and circuit for interleaving data that uses a lookup table to store parameters, a search circuit to determine block size parameters, and a computation circuit to generate address sequences, optimizing the process through iterative intra-row permutations and modular arithmetic techniques like Montgomery reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional circuits implement the 3GPP Turbo code interleaver with hard-wired constant comparators, lookup tables, and multiply/divide logic, then the encoding function is achieved, but the device complexity increases and processing speed decreases
Solution Approach 1:
The patent segments the interleaver circuit into multiple functional units: a parameter determination unit that selects parameters based on block size, a matrix construction unit that organizes data into rows and columns, and an address generation unit that computes permutation addresses. This segmentation allows each unit to be optimized independently and enables pipelining between stages, resolving the contradiction between complexity and speed.
Solution Approach 2:
The patent introduces dynamic parameter selection based on block size classification. Instead of hard-wiring all possible parameter sets, the circuit dynamically selects appropriate parameters (α, β, γ, δ) based on the input block size range. This dynamic approach reduces the overall circuit complexity while maintaining the ability to handle various block sizes efficiently.
2Measurement precision
If the interleaver uses pre-computed sequence vectors stored in memory, then the address sequence generation is accurate, but the loss of time increases due to pre-computation requirements
Solution Approach 1:
The patent pre-classifies block sizes into ranges and pre-determines the corresponding parameters (α, β, γ, δ) for each range. Instead of pre-computing entire address sequences for all possible block sizes, the system pre-prepares parameter sets that can be quickly selected at runtime. This reduces the pre-computation burden while maintaining address sequence accuracy.
Solution Approach 2:
The parameter determination unit uses the block size itself as input to select the appropriate parameters, making the system self-configuring. The circuit automatically determines which parameter set to use based on the incoming data block characteristics, eliminating the need for external pre-computation tables and reducing memory access time.
3Adaptability or versatility
If the circuit implements modular arithmetic with variable modulus for all block sizes, then the interleaving function is complete, but the use of energy increases and processing becomes slower for smaller block sizes
Solution Approach 1:
The patent applies different parameter sets (α, β, γ, δ) to different block size ranges, optimizing the modular arithmetic operations for each specific case. Instead of using a single universal parameter set that works for all block sizes, the circuit selects locally optimized parameters based on the input size, reducing computational energy consumption while maintaining complete interleaving functionality.
Solution Approach 2:
The patent changes the parameters of the modular arithmetic operations based on the block size. By selecting different multipliers (α, β) and divisors (γ, δ) for different block size ranges, the circuit optimizes the computational complexity and energy consumption for each operating condition while preserving the correctness of the interleaving operation.
Data Source
AI summary
According to one aspect of the invention, a method of interleaving data for enabling data coding in a communication network is disclosed, the method including storing parameters required to output address sequences for a matrix, receiving a block size associated with a block of data at a circuit for interleaving data, outputting parameters associated with the stored parameters based upon the block size, and producing an address sequence using the parameters. A circuit for interleaving data for data coding in a communication network is also disclosed. The circuit includes a lookup table storing parameters required to output address sequences for a matrix. A search coupled to the lookup table receives a clock size associated with a matrix and outputs parameters based upon the block size. A computation circuit coupled to receive the parameters outputs an address sequence using the parameters.