Turbo Product Code Decoding With Miscorrection Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing memory systems face miscorrection issues during decoding due to hardware-friendly interleaving, which introduces low-weight codewords and complicates hardware implementation, leading to errors in error correction processes.
Innovation Solution
The proposed solution involves encoding data into codewords arranged in a rectangular array, using techniques such as shortening bits on the diagonal, calculating XOR parities, and permuting bits at column-row intersections to eliminate miscorrection issues, thereby simplifying hardware implementation and improving decoding accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hardware-friendly interleaving is used to simplify hardware implementation, then device complexity is reduced, but miscorrections occur during decoding due to low-weight codewords
Solution Approach 1:
The patent extracts and removes the problematic low-weight codewords from the code structure by shortening specific bits (e.g., diagonal bits) in the codeword array. This extraction eliminates the source of miscorrections while preserving the hardware-friendly interleaving structure, thus maintaining low device complexity without sacrificing decoding reliability.
Solution Approach 2:
The patent applies local quality modification by selectively shortening specific bits at particular positions (such as diagonal elements) in the codeword array rather than uniformly modifying the entire structure. This localized approach eliminates low-weight codewords that cause miscorrections while maintaining the overall hardware-friendly interleaving structure and minimizing impact on device complexity.
2Reliability
If bits are shortened to eliminate low-weight codewords, then miscorrections are eliminated, but codeword structure becomes more complex
Solution Approach 1:
The patent segments the codeword structure into distinct regions, identifying and shortening specific bits (such as diagonal elements) that create low-weight codewords. This segmentation approach systematically eliminates miscorrections by targeting specific problematic positions while maintaining a regular, predictable codeword structure that does not significantly increase overall complexity.
Solution Approach 2:
The patent introduces controlled asymmetry by shortening bits at specific asymmetric positions (e.g., diagonal positions where row index equals column index) in the codeword array. This asymmetric modification selectively eliminates low-weight codewords while maintaining a structured approach that prevents excessive complexity increase in the overall codeword structure.
3Reliability
If XOR parities are calculated and matched to detect miscorrections, then decoding reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the XOR parity calculation and matching operations into the existing decoding process, integrating miscorrection detection functionality with the standard error correction workflow. This merging approach improves decoding reliability through comprehensive parity checking while avoiding the need for separate, complex detection hardware modules.
Solution Approach 2:
The patent implements self-service error detection where the XOR parity mechanism uses the code's own structure and redundancy to automatically detect miscorrections. The parity bits and matching logic leverage the inherent properties of the shortened codeword structure, eliminating the need for external or additional complex detection systems.
Data Source
AI summary
Systems may include a memory storage suitable for storing data, an encoder suitable for encoding data into codewords arranged in an array of a number of rows and a number of columns, and a decoder suitable for receiving the encoded codewords, decoding the encoded codewords, and detecting miscorrections in the decoding.