Turbo Code Bit Collection for Flexible 5G Rate Matching

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Solution Overview

Problem

Current radio communication systems, particularly in fifth-generation cellular systems, face challenges in achieving efficient communication between base station apparatuses and terminal apparatuses due to limitations in coding techniques used in LTE-Advanced Pro and New Radio technologies.

Innovation Solution

The implementation of turbo coding with a coding rate of 1/5, combined with subblock interleaving and bit collection methods, where specific code bit sequences are alternately outputted, and the use of a turbo code internal interleaver to connect constituent encoders in parallel, enhances communication efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If turbo coding with coding rate 1/5 is applied to improve communication reliability, then the communication efficiency is improved, but the device complexity increases due to multiple interleavers and bit collection operations

Engineering Contradiction:
Improvecommunication reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The code bit sequences are divided into five separate sequences (first to fifth code bit sequences) from the turbo coding process, which are then independently interleaved and selectively combined. This segmentation allows for flexible rate matching while maintaining coding reliability, resolving the contradiction between reliability and complexity by organizing the coding output into manageable segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic bit collection that adaptively selects and alternates between different code bit sequences based on the required coding rate. The bit collection unit dynamically adjusts which sequences (second and fourth, or second and fifth) are alternately output, providing flexibility to optimize performance across different communication conditions without fixed complexity constraints.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If subblock interleaver is applied to each code bit sequence to improve error correction performance, then the manufacturing precision of code structure is improved, but the processing time increases

Engineering Contradiction:
Improvecode structure precisionVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The interleaving operation is segmented and applied independently to each of the five code bit sequences rather than to the entire coded sequence. This segmentation enables parallel processing of interleaving operations, maintaining high code structure precision while reducing overall processing time through concurrent execution of interleaver operations on separate sequences.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If bit collection with alternating output of code bit sequences is implemented to achieve flexible rate matching, then the adaptability of coding scheme is improved, but the operation complexity increases

Engineering Contradiction:
Improverate matching flexibilityVSAvoidoperation complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The bit collection unit implements dynamic selection and alternating output of specific code bit sequences (second and fourth, or second and fifth) based on the target coding rate requirements. This dynamic approach provides adaptable rate matching for different communication scenarios while using systematic alternating patterns that simplify the operational complexity compared to arbitrary selection methods.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11265107B2Base station apparatus, terminal apparatus, communication method, and integrated circuit with cyclic redundancy check parity bits attachment
Publication Date: 2022.03.01 SHARP KK
  • US11265107B2 patent drawing
  • US11265107B2 patent drawing
  • US11265107B2 patent drawing

AI summary

Channel encoding is provided that includes applying turbo coding with a coding rate of 1/5 to an input bit sequence, applying a subblock interleaver to each of first to fifth code bit sequences to which the turbo coding is applied, applying bit collection to the first to fifth code bit sequences output from the subblock interleaver, the bit collection outputting the first code bit sequence in order, outputting the second code bit sequence and the fourth code bit sequence alternately on a bit-by-bit basis after the first code bit sequence, and outputting the second code bit sequence and the fifth code bit sequence alternately on a bit-by-bit basis.