Turbo Decoder Buffer Control for Adaptive HARQ Memory Access
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Solution Overview
Problem
Conventional turbo decoders face challenges in high throughput communications systems due to high power consumption and performance degradation, particularly when using external shared HARQ memory and fixed iteration decoding, which affects both cost and system efficiency.
Innovation Solution
A decoding apparatus with adaptive control over an external buffer interface and a turbo decoder, utilizing an on-chip buffer for initial decoding and transmitting code blocks to an off-chip buffer only upon decoding failure, along with an adaptive iteration scheme and hard decision aided CRC verification to optimize power consumption and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data is stored in external shared HARQ memory instead of internal dedicated HARQ memory, then cost is reduced, but power consumption increases and access performance degrades
Solution Approach 1:
The patent divides the HARQ buffer into two segments: an internal HARQ buffer (first buffer) for frequent access and an external HARQ buffer (second buffer) for cost-effective storage. This segmentation allows the system to use the internal buffer for power-intensive operations while using the external buffer for cost-sensitive storage, thereby reducing overall power consumption while maintaining cost efficiency.
Solution Approach 2:
The patent introduces an intermediary mechanism (the internal HARQ buffer) between the turbo decoder and the external HARQ memory. This intermediary allows data to be cached locally for frequent access, reducing the need for repeated accesses to the external memory and thereby lowering power consumption while still benefiting from the cost advantages of external storage.
2Reliability
If data is frequently accessed from external shared HARQ memory, then HARQ mechanism reliability is improved, but system performance degrades due to bus contention
Solution Approach 1:
The patent segments the buffer architecture into internal and external components, allowing the internal buffer to handle frequent access operations and the external buffer to provide reliable storage. This segmentation reduces bus contention by localizing frequent access operations to the internal buffer, thereby maintaining HARQ reliability while improving system performance.
Solution Approach 2:
The patent implements preliminary action by pre-loading data into the internal HARQ buffer before it is needed for decoding operations. This allows the internal buffer to be prepared in advance, reducing the need for frequent accesses to the external memory during critical decoding operations and thereby improving system performance while maintaining reliability.
3Device complexity
If a fixed number of iterations is used for decoding each code block, then system complexity is reduced, but decoding performance is lost in low-power scenarios
Solution Approach 1:
The patent implements a dynamic iteration control mechanism where the number of decoding iterations is adjusted based on decoding outcomes and power consumption conditions. The turbo decoder can adaptively increase or decrease the number of iterations for different code blocks, allowing the system to optimize between complexity and performance dynamically rather than using a fixed iteration count.
Solution Approach 2:
The patent changes the parameter of iteration count from a fixed value to a dynamic parameter that can be adjusted based on system conditions. The turbo decoder monitors decoding progress and power consumption, and accordingly modifies the number of iterations performed for each code block, enabling the system to achieve better decoding performance when needed while reducing complexity in low-power scenarios.
4Use of energy by moving object
If code block based early termination is implemented, then power consumption is reduced, but it is not sufficient for low-power receiver design
Solution Approach 1:
The patent extends the early termination concept by implementing a more dynamic and fine-grained control mechanism. The turbo decoder can terminate decoding at different stages based on intermediate results, power consumption thresholds, and code block characteristics. This dynamic approach allows for more aggressive power saving while maintaining decoding reliability compared to conventional fixed early termination schemes.
Solution Approach 2:
The patent changes the termination parameter from a fixed code block level to a more granular and adaptive parameter that can be adjusted based on decoding progress and power conditions. The system can dynamically adjust the termination point within code blocks and across different code blocks, enabling more effective power consumption reduction while preserving decoding reliability through adaptive parameter modification.
Data Source
AI summary
A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.