Parallel Turbo Decoder Memory Access Using Butterfly Networks
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Solution Overview
Problem
Existing wireless communication systems face challenges in achieving high-speed turbo decoding with low power consumption, particularly in portable devices, due to the need for high clock frequencies and complex multiple access schemes that require large multiplexers and complex algorithms.
Innovation Solution
The implementation of a memory bank with Butterfly networks configured to enable parallel access without memory access conflicts, using a multiple access rule to generate control signals for both linear and interleaved orders, allowing for efficient parallel processing of turbo codes in wireless communication systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency of the receiver decoder is increased to achieve higher data rates, then the decoding speed is improved, but the power consumption increases
Solution Approach 1:
The decoder is divided into multiple parallel processing units (segments) that operate simultaneously at lower clock frequencies. Each unit processes a portion of the data in parallel, achieving high overall throughput without requiring each individual unit to run at high speed, thus reducing power consumption while maintaining decoding speed.
Solution Approach 2:
The solution transitions from a single-threaded sequential processing approach to a multi-threaded parallel processing architecture. By adding the dimension of parallelism (multiple processing units working concurrently), the system achieves high data rates without increasing the clock frequency of individual units, thereby avoiding the associated power consumption increase.
2Speed
If parallel processing is applied for decoding to achieve high data rates, then the decoding speed is improved, but the complexity of multiple access schemes increases
Solution Approach 1:
The memory access problem in parallel processing is segmented by dedicating separate memory banks to different processing units. This segmentation eliminates the need for complex arbitration and multiple access schemes, as each processor has its own memory resource, thereby reducing system complexity while maintaining parallel processing capability.
Solution Approach 2:
The patent introduces an interleaver as an intermediary component that prepares data in a specific pattern before it reaches the parallel processing units. This intermediary structure ensures that each processing unit receives data in a predictable, non-conflicting sequence, simplifying the memory access scheme and reducing the need for complex control logic.
3Productivity
If an interleaver is designed to support multiple access schemes for parallel processing, then parallel processing capability is improved, but the adaptability to different systems is reduced
Solution Approach 1:
The patent employs a universal memory bank structure that can serve multiple processing units with different access patterns. The memory banks are designed to be agnostic to the specific interleaving scheme used, allowing the same memory infrastructure to support various parallel processing configurations and different system requirements, thereby maintaining both parallel processing capability and system adaptability.
4Productivity
If large switches (multiplexers) are used to implement multiple access in parallel decoders, then parallel access capability is improved, but the device complexity and area increase
Solution Approach 1:
Instead of using a single large multiplexer to handle all memory access, the system segments memory access into multiple dedicated memory banks, each accessed by specific processing units. This segmentation eliminates the need for large complex switches, as each memory bank has a simpler, dedicated access path, thereby reducing device complexity and area while maintaining parallel access capability.
Data Source
AI summary
A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks in accordance with a multiple access rule to enable parallel access to the memory bank, without memory access conflict, for one of a linear order and an interleaved order. The method and apparatus is particularly advantageous for use in turbo decoding.