Turbo Decoder Circular Pipeline for Contention-Free Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The HSPA+ standard's Turbo Convolution Code (TCC) decoding process faces significant computational intensity and resource requirements, leading to inefficient processing unit utilization due to contention issues and idle cycles, which are exacerbated by the need for parallel processing across multiple units without a contention-free interleaver.
Innovation Solution
A circular pipeline architecture is implemented, where each data block undergoes consecutive half-iterations on different processing units, eliminating idle cycles and allowing for parallel processing without physical division of data blocks, thereby utilizing processing units more efficiently and reducing memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing units are used to process data blocks in parallel, then throughput is improved, but memory requirements increase significantly
Solution Approach 1:
The patent segments the processing of data blocks across multiple pipeline stages, where each stage processes a different iteration of the decoding algorithm. This allows parallel processing of different blocks at different pipeline stages while reusing the same processing units, thereby improving throughput without proportionally increasing memory requirements.
Solution Approach 2:
The patent implements a nested structure where multiple data blocks are nested within the pipeline stages. Each pipeline stage contains multiple blocks at different processing iterations, allowing efficient memory utilization while maintaining high throughput through parallel processing.
2Quantity of substance
If a single processing unit performs consecutive SISO operations on a data block, then memory requirements are reduced, but idle cycles increase due to write back delays
Solution Approach 1:
The patent ensures continuity of useful action by pipelineing the processing across multiple stages. While one stage is performing SISO operations on a data block, another stage simultaneously performs write back operations on a different block, eliminating idle cycles and maintaining continuous productive work across the system.
Solution Approach 2:
The patent introduces a temporal dimension to the processing architecture by organizing operations across multiple pipeline stages that operate at different times. This allows write back operations to be performed in parallel with SISO operations on different blocks, converting sequential delays into parallel opportunities.
3Productivity
If data blocks are divided across multiple processing units, then parallel processing capability is improved, but contention for memory access increases
Solution Approach 1:
The patent applies preliminary action by pre-organizing data blocks into distinct pipeline stages before processing begins. Each stage is assigned specific blocks and iterations in advance, which eliminates runtime contention for memory access by ensuring that processing units access different memory locations at different times without conflict.
Data Source
AI summary
In one embodiment, a method of block decoding is provided. For each of a plurality of data blocks input to a memory arrangement, a plurality of decoding iterations are performed using a circular pipeline of processing stages. For each decoding iteration, one processing stage of the circular pipeline performs a first set and a second set of soft-input-soft-output (SISO) decoding operations on a block of data. The first set of SISO decoding operations produces an intermediate block of data. The second set of SISO decoding operations is performed on the intermediate data block to complete the one decoding iteration. The next decoding iteration of the plurality of decoding iterations is performed using the next processing stage following the one processing stage of the circular pipeline of processing stages.