Turbo Decoder Interleaver Addressing With Stored Column Indexes
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Solution Overview
Problem
Turbo decoders face challenges with excessive time and redundant logic in regenerating interleaver addresses during decoding, and the need to generate multiple interleaver addresses out of order and identify out-of-bounds addresses per cycle, which increases memory demands and power consumption.
Innovation Solution
Storing only the column indexes in a RAM allows for efficient calculation of interleaved addresses and dummy entry locations, reducing the need for repeated interleaving sequence computation and minimizing memory requirements, enabling multiple addresses and out-of-bounds identification per cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interleaver sequence is regenerated during decoding, then the turbo decoder can reverse the interleaving process, but excessive time and redundant logic are required
Solution Approach 1:
The interleaver sequence is pre-calculated and stored in a lookup table before decoding operations. During decoding, the turbo decoder directly retrieves the stored sequence instead of regenerating it, which eliminates redundant computation and reduces logic complexity while maintaining decoding functionality
Solution Approach 2:
Instead of regenerating the interleaver sequence through complex logic, the patent uses a stored copy of the sequence in a lookup table. This copying approach replaces computational logic with simple memory retrieval, significantly reducing the time and logic required during decoding operations
2Productivity
If multiple interleaver addresses are generated out of order per cycle, then parallel processing throughput is increased, but memory demands increase
Solution Approach 1:
The patent segments the address generation process by using separate column and row counters that independently track position within the interleaver matrix. This segmentation allows multiple addresses to be generated in parallel without requiring a single large memory structure, as each counter operates within its own segmented space
Solution Approach 2:
The patent transforms the one-dimensional address generation problem into a two-dimensional solution using row and column counters. By adding the dimensional aspect of row-column indexing, the system can generate multiple addresses per cycle through coordinate computation rather than sequential memory access, increasing throughput without proportionally increasing memory demands
3Speed
If multiple interleaver addresses are generated out of order per cycle, then processing speed is increased, but out-of-bounds detection becomes more complex
Solution Approach 1:
The patent implements feedback mechanisms where the row and column counters continuously monitor their own values against predefined limits. When counters approach boundary conditions, the feedback logic automatically detects out-of-bounds conditions and adjusts address generation accordingly, enabling fast parallel processing with simplified detection logic
Solution Approach 2:
The counter system performs self-detection of out-of-bounds conditions by comparing counter values against stored matrix dimensions. This self-service approach eliminates the need for complex external detection logic, as the counters inherently know their boundaries and can autonomously identify when addresses fall outside valid ranges
4Ease of operation
If the full interleaver sequence is stored in memory, then address generation is simplified, but memory usage increases
Solution Approach 1:
The patent extracts only the essential column index information from the full interleaver sequence and stores only this condensed data in memory. The row information is generated on-demand through counters during address generation. This extraction approach simplifies address generation while minimizing memory usage by storing only what is necessary
Data Source
AI summary
A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. An address generator generates the regenerated interleaver sequence based on the column indexes and computed data. In embodiments the address generator can read column indexes from the addressable column index memory, compute the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data, combine the column indexes so read and the row indexes so permuted, use a row counter, and identify out of bounds addresses using the regenerated interleaver sequence.