Turbo Decoder Core Scheduling for Load-Balanced Throughput

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Solution Overview

Problem

Existing turbo decoder systems with multiple cores face inefficiencies in decoding throughput due to uneven processing loads and resource constraints, leading to increased decoding time and hardware complexity, especially in high-speed data transmission systems like LTE.

Innovation Solution

A method and apparatus that computes the remaining decoding times for each decoder core and allocates packets to the core with the shortest remaining decoding time, utilizing an Arithmetic Logic Unit (ALU) to monitor and manage resource distribution efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple decoder cores are used to increase decoding throughput, then productivity is improved, but device complexity increases due to uneven processing loads and resource management requirements

Engineering Contradiction:
Improvedecoding throughputVSAvoidresource management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic load balancing by continuously monitoring the remaining decoding time of each decoder core and dynamically assigning new packets to the core with the shortest remaining time. This dynamic adaptation ensures optimal resource utilization and balances the processing load across multiple cores, resolving the contradiction between improved productivity and increased device complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms by computing and comparing the remaining decoding times of all decoder cores before each packet assignment. This feedback loop allows the controller to make informed decisions about packet allocation, ensuring that the workload is distributed efficiently across cores based on their current status, thereby managing complexity while maintaining high throughput.

Inventive Principle:
Principle #23Feedback

2Device complexity

If packets are assigned sequentially to decoder cores without considering processing conditions, then device complexity is reduced, but productivity decreases due to uneven processing loads and increased decoding time

Engineering Contradiction:
Improveresource allocation simplicityVSAvoiddecoding throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent transitions from static sequential assignment to dynamic load-aware assignment. The system continuously adapts packet allocation decisions based on real-time monitoring of decoder core status, specifically the remaining decoding time. This dynamic approach optimizes throughput by ensuring that packets are always assigned to the most available core, preventing idle time and balancing the workload effectively.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the allocation parameter from fixed sequential order to variable selection based on remaining decoding time. By using the remaining time metric as the selection criterion, the system optimizes packet assignment to minimize total decoding time and maximize throughput, directly addressing the productivity loss caused by simple sequential assignment.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9369236B2Decoding apparatus and method
Publication Date: 2016.06.14 SAMSUNG ELECTRONICS CO LTD
  • US9369236B2 patent drawing
  • US9369236B2 patent drawing
  • US9369236B2 patent drawing

AI summary

The present disclosure relates to a turbo decoder and decoding method thereof. The turbo decoder has a plurality of decoder cores. The decoding method includes: computing remaining decoding times for the multiple decoder cores; selecting a decoder core with the shortest remaining decoding time among the multiple decoder cores; and allocating a packet to the selected decoder core. The decoder cores of the turbo decoder are monitored in real time and resources are distributed through efficient decoder core selection enhancing decoding throughput.