Turbo Decoder Extrinsic Addressing for Conflict-Free Parallel Memory Access
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Solution Overview
Problem
Turbo decoders face memory conflicts when multiple decoder engines access the same extrinsic RAM in a parallel architecture, leading to decoding errors, particularly in high-speed applications like 3GPP cellular specifications.
Innovation Solution
The solution involves organizing extrinsic values in extrinsic RAMs such that each decoder engine operates on unique rows or columns, using a conflict-free address generator to ensure that each engine accesses different data during both linear and interleaved MAP estimates, thereby preventing memory conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple decoder engines access the same extrinsic RAM in parallel, then processing speed increases, but memory conflicts occur leading to decoding errors
Solution Approach 1:
The extrinsic RAM is segmented into multiple banks, with each bank dedicated to specific decoder engines. This segmentation prevents memory conflicts by ensuring that each engine accesses only its designated bank, eliminating simultaneous access conflicts while maintaining parallel processing capability
Solution Approach 2:
Different regions of the extrinsic RAM are allocated with different access patterns and timing characteristics tailored to specific decoder engines. Each engine has its own local memory space with optimized access parameters, allowing high-speed parallel operation without interference
2Productivity
If extrinsic values are stored in extrinsic RAM for parallel access, then decoding throughput increases, but memory conflicts cause data errors
Solution Approach 1:
The system pre-allocates and pre-organizes extrinsic values in the extrinsic RAM before parallel decoding begins. Address generators are pre-configured with conflict-free addressing schemes, ensuring that during parallel operation, each engine reads and writes to predetermined locations without potential for conflict
Solution Approach 2:
Address generators act as intermediaries between decoder engines and extrinsic RAM. These intermediaries translate engine requests into conflict-free memory addresses, managing the interface between parallel processing demands and memory access constraints to prevent data corruption
3Speed
If a parallel architecture with multiple decoder engines is used, then high data rate processing is achieved, but memory access conflicts increase
Solution Approach 1:
The memory architecture adds a bank dimension to the address space, organizing extrinsic RAM into multiple banks that can be accessed simultaneously. This dimensional expansion allows multiple decoder engines to operate in parallel without conflicts, as each engine can access different banks at the same time
Data Source
AI summary
A plurality of turbo decoder engines store extrinsic values when concurrently decoding a received signal encoded within rows and columns of an interleaving matrix where interleaved values stay in a same re-ordered row during interleaving. An extrinsic reader and extrinsic writer accesses extrinsic memories using extrinsic addresses. A deinterleaver accesses the extrinsic addressable memories by arranging storage of the extrinsic values by the same rows of the same interleaving matrix that was used to encode the received signal, each of the rows corresponding to one of the plurality of turbo decoder engines, and, in embodiments, can group the extrinsic values such that all the extrinsic values in each one of the rows of the interleaving matrix go in a same one of the plurality of the extrinsic addressable memory. The deinterleaver can skip read of extrinsic values corresponding to dummy entries in the interleaving matrix.