Turbo Decoder Iteration Limits for Lower Decoding Latency

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Solution Overview

Problem

Turbo decoders in integrated circuit devices have high compute complexity, leading to significant decoding latency in Turbo equalizers, which is undesirable and needs to be reduced.

Innovation Solution

Limiting the number of decoder loop iterations in Turbo decoders to a set number less than optimal for bit error rate (BER), resulting in a controlled BER penalty, to reduce decoding latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of decoder loop iterations is increased to achieve optimal bit error rate, then decoding reliability is improved, but decoding latency increases

Engineering Contradiction:
Improvebit error rateVSAvoiddecoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing a limited number of decoding iterations (e.g., 1-3 iterations) instead of the full optimal number of iterations. This partial execution reduces the computational burden and latency while accepting a controlled BER penalty, thereby resolving the contradiction between reliability and time loss.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If the number of decoder loop iterations is increased to achieve optimal bit error rate, then decoding reliability is improved, but device complexity increases

Engineering Contradiction:
Improvebit error rateVSAvoidcompute complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent reduces device complexity by performing only a subset of the required decoding iterations. By executing partial iterations (e.g., 1-3 instead of optimal iterations), the computational complexity of the Turbo decoder is significantly reduced while maintaining acceptable decoding reliability through the outer decoding loop.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8522119B2Reduction in decoder loop iterations
Publication Date: 2013.08.27 XILINX INC
  • US8522119B2 patent drawing
  • US8522119B2 patent drawing
  • US8522119B2 patent drawing

AI summary

An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.