Turbo Decoder Memory Arbitration for Interleaver Bank Conflicts
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Solution Overview
Problem
Parallel turbo decoders face access contention issues in shared interleaver memory, leading to performance bottlenecks due to simultaneous access conflicts, which can result in reduced coding gain and susceptibility to jamming, especially when using conflict-free interleavers that may not be suitable for all degrees of parallelism.
Innovation Solution
The implementation of a memory arbitrator with buffer memories associated with each subdecoder to reschedule accesses to the shared interleaver memory, preventing simultaneous access to a single bank by buffering and delaying conflicting access attempts, thereby avoiding conflicts and optimizing interleaver memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel decoding is used to increase decoding speed, then productivity is improved, but access contention in shared interleaver memory increases causing performance bottlenecks
Solution Approach 1:
The shared interleaver memory is divided into multiple banks, and buffer memories are associated with each subdecoder to segment the memory access paths. This segmentation allows multiple subdecoders to access different banks simultaneously, reducing access contention while maintaining parallel decoding throughput.
Solution Approach 2:
Buffer memories are introduced as intermediary components between subdecoders and the shared interleaver memory. These buffers temporarily store data and resolve timing conflicts, allowing subdecoders to proceed in parallel without waiting for memory access completion, thereby eliminating the performance bottleneck.
2Reliability
If conflict-free interleavers are used to avoid access contention, then reliability is improved, but adaptability to different degrees of parallelism deteriorates
Solution Approach 1:
The system dynamically adapts to different degrees of parallelism by configuring the number of buffer memories and memory banks according to the specific parallel decoding requirement. This dynamic configuration allows the same architecture to maintain both conflict-free operation and adaptability across various parallelism levels.
Solution Approach 2:
The architecture allows changing key parameters such as the number of buffer memories, bank count, and buffer depth to optimize performance for different parallelism degrees. By adjusting these parameters, the system maintains coding gain while adapting to various parallel decoding configurations.
3Productivity
If multiport memories are used to reduce memory bottleneck, then productivity is improved, but device complexity increases
Solution Approach 1:
Instead of using a complex multiport memory structure, the patent segments the memory system into multiple single-port memory banks with associated buffers. This segmentation achieves similar throughput improvement while using simpler, more readily available single-port memory components.
Solution Approach 2:
The patent creates multiple copies of the buffer memory structure, one for each subdecoder, rather than implementing a single complex multiport memory. This copying approach simplifies the overall memory structure while maintaining the ability to serve multiple subdecoders in parallel.
Data Source
AI summary
A technique for resolving access contention in a parallel turbo decoder is described. The technique includes associating a plurality of buffer memories with the subdecoders so that accesses to banks of a shared interleaver memory can be rescheduled. Accesses can be rescheduled to prevent simultaneous accesses to a single bank of the shared interleaver memory based on an interleaver pattern.