Parallel Turbo Decoder Routing Without Address Networks

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Solution Overview

Problem

Turbo codes in communication systems face high decoding complexity and latency, which are exacerbated by the physical size, power consumption, and connectivity overhead of traditional address routing networks in parallel Turbo decoders used in battery-powered devices.

Innovation Solution

Eliminating address routing networks and moving address generation from processors to dedicated modules, thereby reducing circuit area, power consumption, and latency, and using a data routing network to facilitate efficient data transfer between processors and memory banks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If address routing networks are used in parallel Turbo decoder, then data can be routed between processors and memory banks, but circuit area and power consumption increase

Engineering Contradiction:

Improvedata routing capabilityVSAvoidcircuit area

Core Design Contradiction:

Ease of operationVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the address routing network from the parallel Turbo decoder architecture. Instead of using a complex address routing network to map processor addresses to memory bank addresses, the system uses a simplified direct mapping scheme where each processor is directly connected to specific memory banks without requiring address translation infrastructure.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The data routing network is designed to handle multiple functions simultaneously - it routes both address information and data between processors and memory banks using the same physical infrastructure, eliminating the need for separate address routing networks and reducing overall circuit area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of operation

If address routing networks are used in parallel Turbo decoder, then data can be routed between processors and memory banks, but power consumption increases

Engineering Contradiction:

Improvedata routing capabilityVSAvoidpower consumption

Core Design Contradiction:

Ease of operationVSUse of energy by stationary object

Solution Approach 1:

The patent removes the address routing network that would consume power, replacing it with a combinatorial address mapping function that requires no active routing infrastructure. This eliminates the dynamic power consumption associated with address signal switching and routing through multiple logic stages.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The address mapping relationships are predetermined and hardwired into the system architecture during design, eliminating the need for runtime address calculation and routing decisions. This preliminary configuration of address mappings removes the need for active address routing logic during operation, reducing power consumption.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If address generation is performed by processors, then flexibility is maintained, but processing time and latency increase

Engineering Contradiction:

Improveaddress generation flexibilityVSAvoidprocessing latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent separates address generation from processor operations by creating dedicated address generation units for each processor. These units operate in parallel with the main processing logic, generating addresses independently without blocking processor execution. This segmentation allows address generation to occur simultaneously with data processing, eliminating latency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces dedicated address generation units as intermediary components between processors and memory banks. These units handle all address generation and mapping operations, allowing processors to focus on data processing while the intermediary address units handle memory address calculation, thereby reducing processor latency and maintaining flexibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Ease of operation

If complex routing networks are used, then data can be routed between processors and memory banks, but connectivity overhead increases

Engineering Contradiction:

Improvedata routing capabilityVSAvoidconnectivity overhead

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent extracts and removes the address routing network from the system, eliminating the complex connectivity infrastructure required for address translation. This leaves only the essential data routing paths between processors and memory banks, significantly reducing connectivity overhead while maintaining data routing capability through simplified direct connections.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS8327058B2Method and system for routing data in a parallel turbo decoder

Publication Date: 2012.12.04 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power consumption, and/or latency of parallel Turbo decoders. According to certain aspects of the present invention, address routing-networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from the processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency.