Turbo Decoder Trellis Selection for Arbitrary Code Rates
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Solution Overview
Problem
Turbo decoders with conventional trellises face limitations in high-throughput requirements for arbitrary code rate operations due to long decoding latency and large circuit area, especially when dealing with non-periodically punctured codes.
Innovation Solution
A method and device for de-puncturing turbo-coded digital data using a trellis controller and zero-patch module to determine the appropriate decoding trellis and insert zeros into the systematic and parity check codes, allowing for the use of reciprocal dual trellises to enhance decoding speed and efficiency across various code rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional trellises are used in turbo decoders, then decoding can be performed with standard circuit implementation, but decoding latency becomes long and circuit area becomes large for high-throughput requirements
Solution Approach 1:
The patent applies dynamics by making the trellis structure adaptable and configurable. The decoding trellis can be dynamically selected between conventional trellis and reciprocal dual trellis based on the code rate being decoded. This dynamic adaptation allows the system to optimize for speed (using reciprocal dual trellis for high code rates) or standard compatibility (using conventional trellis for low code rates), thereby resolving the contradiction between throughput and latency.
Solution Approach 2:
The patent changes the structural parameters of the decoding trellis by introducing reciprocal dual trellis as an alternative configuration. This parameter change involves inverting the direction of transitions in the trellis diagram, which fundamentally alters the decoding path and enables faster processing for certain code rates. By changing this structural parameter, the system achieves high throughput without sacrificing decoding accuracy.
2Productivity
If conventional trellises are used in turbo decoders, then standard decoding algorithms can be applied, but circuit area becomes large for high-throughput operations
Solution Approach 1:
The system dynamically configures the trellis structure based on operational requirements. When high throughput is needed, the reciprocal dual trellis is activated, which has a more efficient circuit implementation for parallel processing. This dynamic reconfiguration allows the circuit area to be optimized for the current operating mode, reducing the overall circuit area requirement while maintaining high throughput capability.
Solution Approach 2:
The patent creates a universal decoding system that can handle multiple code rates efficiently by supporting both conventional and reciprocal dual trellis configurations. This multi-functionality allows a single circuit design to adapt to different throughput requirements and code rate scenarios, eliminating the need for separate dedicated circuits for each operation mode, thereby reducing total circuit area.
3Reliability
If zeros are inserted into punctured bits to reconstruct original codes, then the code length is extended to non-punctured length, but the depuncturing process becomes complex for non-periodical puncturing
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the positions of punctured bits according to the puncturing pattern (whether periodical or non-periodical). Before the actual depuncturing operation, the system has already prepared a map or indicator sequence that marks where zeros should be inserted. This preliminary preparation simplifies the depuncturing process significantly, as the system only needs to follow the pre-computed positions rather than determining them in real-time, thereby reducing complexity while maintaining reconstruction accuracy.
4Productivity
If different decoding trellises are selected based on code rate, then decoding efficiency is improved across various code rates, but the system requires a trellis controller to manage selection
Solution Approach 1:
The trellis controller manages parameter changes by selecting between different trellis configurations (conventional or reciprocal dual) based on the code rate parameter. This parameter-driven selection mechanism allows the system to adapt its decoding structure to match the input code characteristics. The controller's complexity is justified by the significant gains in decoding efficiency achieved through optimal trellis selection for each code rate scenario.
Solution Approach 2:
The system employs feedback by monitoring the code rate of the incoming turbo-coded data and using this information to select the appropriate decoding trellis. The trellis controller receives feedback about the code rate and adjusts the trellis configuration accordingly. This feedback loop ensures that the most efficient decoding path is always used, maximizing productivity while keeping the controller's decision-making process simple and rule-based.
Data Source
AI summary
A turbo decoder system decodes L-length digital data consisting of a systematic code and 1st and 2nd parity check codes, and includes a trellis controller obtaining the ratio of the bit-number Ep of the 1st/2nd parity check code to the bit-number D of an original systematic code and generating, based on the code rate of the digital data, a trellis control output indicating a target decoding trellis, which is selected by a turbo decoder to perform decoding operations. A zero-patch module patches zeros into the systematic code, and patches, based on the value of Ep/D, one or more zeros into the 1st/2nd parity check code so that parity check bits of the 1st/2nd parity check code and the zero-bit(s) form a periodically depunctured parity check code.