Turbo Decoder Interleaving Buffers for Write Conflict Handling
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Solution Overview
Problem
High-throughput turbo-decoding systems face write access conflicts due to the need for concurrent interleaving and de-interleaving of Log-Likelihood Ratios (LLRs) in wireless communication systems, particularly in CDMA systems, where the complexity of hardware increases exponentially with the number of producers, making it impractical to use N-port RAMs effectively.
Innovation Solution
A concurrent interleaving architecture that processes output data from N producers, using a stalling mechanism to manage write access by selecting a subset of output data for storage in a register bank and writing it to target memories, reducing hardware complexity by leveraging statistical properties of pseudo-random interleavers, where the average number of write accesses to a buffer is significantly lower than the worst case, and employing binary-tree based parallel scan operations to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If N-port RAMs are used to handle concurrent write accesses from N producers, then write access conflicts are resolved, but hardware complexity increases exponentially
Solution Approach 1:
The patent divides the N producers into multiple groups, with each group writing to a separate target memory. This segmentation reduces the number of concurrent write accesses to each memory, allowing the use of single-port RAMs instead of complex N-port RAMs, thereby resolving write access conflicts without exponential hardware complexity increase
Solution Approach 2:
The patent introduces an interleaver as an intermediary component that redistributes LLRs from N producers to multiple target memories. The interleaver acts as a mediator that manages the concurrent write accesses, preventing direct conflicts at the memory ports while maintaining the required throughput and functionality
2Productivity
If multiple LLRs are read and written concurrently to achieve high throughput, then processing speed increases, but write access conflicts increase
Solution Approach 1:
The patent segments the target memories into multiple separate memory units, each handling a subset of the concurrent write accesses. This segmentation allows multiple LLRs to be written concurrently to different memories without conflicts, maintaining high throughput while reducing conflict frequency at each memory port
Solution Approach 2:
The patent resolves the conflict by adding a spatial dimension - distributing writes across multiple memory units rather than concentrating them at a single memory port. This dimensional distribution allows concurrent accesses to proceed without interference, achieving both high throughput and low conflict frequency
Data Source
AI summary
A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.