Turbo Decoding with Circular Sub-Blocks for Parallel Metrics
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Solution Overview
Problem
Turbo decoders face decoding delays due to sequential calculation of forward and backward metrics, which reduces decoding speed and increases complexity, especially in iterative processes, and existing parallel decoding schemes either insert tail bits or require additional metric calculations, degrading performance.
Innovation Solution
The method involves dividing an information frame into sub-blocks, encoding each sub-block independently, and applying a circular encoding scheme to maintain metric reliability without additional bit insertion, allowing for parallel calculation of metrics across sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential calculation of forward and backward metrics is used in turbo decoding, then decoding accuracy is maintained, but decoding speed decreases and complexity increases
Solution Approach 1:
The patent divides the information frame into multiple sub-blocks and processes each sub-block independently through parallel decoding operations. This segmentation allows simultaneous calculation of forward and backward metrics for different sub-blocks, significantly increasing decoding speed while maintaining accuracy through independent processing of each segment
Solution Approach 2:
The patent introduces a new dimension of parallel processing by organizing decoding operations across multiple sub-blocks simultaneously. Instead of sequential single-threaded processing, the system creates a parallel processing architecture where multiple decoding paths operate concurrently, effectively adding a temporal parallelism dimension to the decoding process
2Productivity
If parallel decoding schemes are used to increase decoding speed, then decoding speed improves, but performance degrades due to tail bit insertion or additional metric calculations
Solution Approach 1:
The information frame is segmented into multiple sub-blocks that can be decoded in parallel. Each sub-block is processed independently without requiring tail bit insertion, as the circular encoding scheme allows seamless parallel processing. This segmentation enables speed improvement while avoiding the performance degradation associated with traditional parallel schemes
Solution Approach 2:
The patent changes the encoding parameter structure by using circular encoding where the terminal state of one sub-block connects to the initial state of the next sub-block. This parameter change eliminates the need for additional tail bits or guard periods, allowing true parallel processing without performance loss
3Productivity
If circular encoding scheme is applied to enable parallel processing, then decoding speed increases and band efficiency is maintained, but implementation complexity increases
Solution Approach 1:
The patent segments the decoding process into independent sub-block operations that can be executed in parallel. Each sub-block processor operates autonomously with identical logic, simplifying the overall implementation despite the parallel architecture. The segmentation creates modular, repeatable units that reduce implementation complexity through standardization
Solution Approach 2:
The patent uses identical decoding logic copied across multiple sub-block processors. Each sub-block uses the same forward and backward metric calculation algorithms, creating a replicated processing structure. This copying approach simplifies implementation by reusing proven code and logic rather than developing complex custom solutions for each processing element
Data Source
AI summary
A method and apparatus for turbo encoding and method and apparatus for turbo decoding are disclosed, by which encoding and decoding speeds of turbo codes and performance thereof can be enhanced. In performing turbo encoding on inputted information bits by a unit of an information frame including a predetermined number of bits, the present invention includes dividing the information frame into at least two information sub-blocks, encoding each of the at least two information sub-blocks independently, rearranging information bits configuring the information frame by interleaving the information frame, dividing the rearranged information frame into at least two information sub-blocks, and encoding each of the at least two information sub-blocks independently.