Turbo Product-Code Decoding with Parallel Symbol-Group Processing
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Solution Overview
Problem
Current turbo decoding architectures face challenges in achieving high data-processing rates and reducing latency, particularly in high-speed contexts, due to bulky memory requirements and excessive latency in both sequential and pipeline architectures.
Innovation Solution
The proposed solution involves processing all line and column vectors in symbol groups simultaneously, eliminating the need for memory planes between half-iterations, and using a modular decoding device with dynamic interconnection networks to facilitate parallel processing, thereby increasing data-processing rates and reducing overall latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential or pipeline decoding architectures are used, then decoding functionality is achieved, but data-processing rate is limited and latency is excessive
Solution Approach 1:
The matrix to be decoded is divided into multiple sub-matrices, each of which is decoded independently and simultaneously by separate decoding units. This segmentation enables parallel processing of multiple data blocks, significantly increasing the overall data-processing rate while reducing the time required to complete decoding operations.
Solution Approach 2:
The patent transitions from sequential single-threaded decoding to multi-dimensional parallel processing by organizing decoding units in a pipelined architecture that processes multiple sub-matrices simultaneously across different stages. This dimensional expansion of processing capability allows the system to achieve high data-processing rates (exceeding 10 Gbits/s) while maintaining low latency through concurrent operation of multiple decoding paths.
2Ease of manufacture
If memory planes are used to store intermediate matrices, then encoding/decoding can be performed, but device size and material costs increase
Solution Approach 1:
The patent employs buffer memory that pre-stores syndromes and other decoding parameters before they are needed during the actual decoding process. This preliminary preparation of data allows the decoding units to operate continuously without requiring large memory planes for intermediate storage, thereby reducing device size while maintaining complete encoding/decoding functionality.
Solution Approach 2:
Instead of storing complete intermediate matrices in large memory planes, the patent uses buffer memory to store only essential syndrome information and parameters that are copied and reused by multiple decoding units. This selective copying approach minimizes memory requirements while ensuring all decoding operations have access to necessary data.
Data Source
AI summary
The invention relates to a method of decoding a matrix built from concatenated codes, corresponding to at least two elementary codes, with uniform interleaving, the matrix having n1 lines, n2 columns and n1*n2 symbols, the method comprising processing all the lines- and columns-vectors of the matrix by symbol groups, the processing comprising a first decoding to simultaneously process all the symbols of a group of symbols according to their lines and then a second decoding to simultaneously process all the symbols of said group of symbols according to their columns, the symbol groups being thus successively processed in lines and in columns, or conversely.