Turbo Encoder Tail-Bit Allocation for 5G Data Block Reliability

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Solution Overview

Problem

Current wireless communication systems face challenges in efficiently processing data blocks in next-generation 5G systems, particularly in scenarios requiring high spectrum efficiency, ultra-reliability, and massive connectivity, where existing coding schemes struggle to optimize data transmission and reception.

Innovation Solution

The proposed method involves using a turbo encoder with a code rate of 1/5 or 1/3, employing trellis termination to generate tail bits, and performing rate matching through puncturing or repetition, along with interleaving and interlacing of parity bits, to optimize data block processing in user equipment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional coding schemes are used for data block processing in 5G systems, then device complexity is reduced, but coding gain and spectral efficiency deteriorate

Engineering Contradiction:
Improvecoding gainVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The data block is divided into multiple code blocks, each processed by separate constituent encoders in parallel. This segmentation allows the system to achieve high coding gain through multiple encoding paths while managing complexity by distributing processing across independent units rather than requiring a single complex processor.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a time-dimensional processing approach by generating and deploying tail bits to multiple encoded bit sequences (first, second, and third sequences) at different stages. This temporal dimension allows the system to accumulate coding gain across multiple transmission opportunities while maintaining manageable instantaneous processing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If high code rate encoders are used to increase data transmission efficiency, then productivity increases, but reliability deteriorates due to reduced redundancy

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoiderror correction capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Tail bits are generated through trellis termination before the actual data transmission begins. This preliminary generation of redundancy bits ensures that error correction capability is established in advance, allowing the system to use higher code rates for improved throughput while maintaining reliability through pre-configured redundancy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the code rate by selecting between different encoder configurations (1/3, 2/3, 3/4, 4/5 code rates) based on channel conditions and service requirements. This parameter change capability allows the system to optimize the balance between productivity and reliability by adapting the redundancy level to actual transmission needs.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If fixed encoding schemes are used for all data block sizes, then device complexity is reduced, but adaptability deteriorates for different 5G service scenarios

Engineering Contradiction:
Improveservice scenario adaptabilityVSAvoidencoding scheme complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The encoding scheme is made dynamic by allowing the system to select different code rates (1/3, 2/3, 3/4, 4/5) and different numbers of constituent encoders (2 or 3) based on data block size and service requirements. This dynamic adaptation enables the system to handle diverse 5G scenarios (eMBB, uMTC, mMTC) effectively while managing complexity through standardized encoder modules that can be configured differently.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10523386B2Method of processing data block in wireless communication system and apparatus therefor
Publication Date: 2019.12.31 LG ELECTRONICS INC
  • US10523386B2 patent drawing
  • US10523386B2 patent drawing
  • US10523386B2 patent drawing

AI summary

A method for processing a data block by a user equipment in a wireless communication system comprises generating tail bits of 18 bits by performing trellis termination in a turbo encoder of code rate 1/5 containing a plurality of constituent encoders; and deploying the tail bits of 18 bits to 5 encoded bit sequences of the turbo encoder according to a prescribed rule, wherein 4 tail bits are deployed to a systematic bit sequence among the 5 encoded bit sequences according to the prescribed rule, and 4 tail bits are deployed to each of specific 2 parity bit sequences among 4 parity bit sequences according to the prescribed rule.