Turbo Equalizer LLR Exchange With Threshold-Limited Loop-Back

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Solution Overview

Problem

Low-density parity-check (LDPC) codes used in storage applications face challenges in efficient error correction due to performance degradation and hardware complexity issues in turbo equalization processes, particularly in representing and processing soft information values with limited bits, leading to mismatches and correlation problems.

Innovation Solution

Implementing a turbo equalizer system with a soft-input soft-output (SISO) equalizer and decoder that uses a limiter to set a predefined threshold for loop-back signals, reducing mismatches by limiting the magnitude of soft information values and ensuring accurate extrinsic information exchange, thereby improving system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If soft information values are represented with limited bits in turbo equalization, then hardware complexity is reduced, but performance degradation occurs due to mismatches and correlation problems

Engineering Contradiction:
Improvehardware complexityVSAvoiderror correction performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the number of bits used to represent soft information values based on signal conditions. The system transitions between different precision levels (e.g., 4-bit, 6-bit, 8-bit representations) of log-likelihood ratios depending on the reliability of the received signal, thereby optimizing the trade-off between hardware complexity and error correction performance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements dynamics by making the bit representation of soft information adaptive rather than fixed. The turbo equalizer dynamically selects the precision level for storing and processing LLR values based on signal-to-noise ratio measurements and iteration count, allowing the hardware to operate efficiently across varying channel conditions without sacrificing reliability

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If extrinsic information is exchanged between SISO equalizer and decoder, then error correction accuracy is improved, but hardware requirements increase

Engineering Contradiction:
Improveerror correction accuracyVSAvoidhardware requirements
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the extrinsic information exchange into separate processing stages within the turbo equalizer architecture. The SISO equalizer and SISO decoder are implemented as distinct modules that exchange processed information through defined interfaces, allowing each component to be optimized independently while maintaining overall system accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the parameter of information representation by using compact mathematical formulations for extrinsic information calculation. Instead of exchanging full probability distributions, the system exchanges condensed log-likelihood ratio values that capture the essential information with reduced bit requirements, thereby lowering hardware complexity while preserving accuracy

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8489973B1Numerical solution on LLR exchange in turbo equalization
Publication Date: 2013.07.16 SK HYNIX MEMORY SOLUTIONS AMERICA INC
  • US8489973B1 patent drawing
  • US8489973B1 patent drawing
  • US8489973B1 patent drawing

AI summary

The present application refers to a method for determining an extrinsic information input to an ECC decoder of a turbo equalizer. In one embodiment, a first loop-back signal is represented with a first number of bits, wherein the first loop-back signal comprises a signal looped back from an output of an ECC decoder. An output of a signal detector is represented with a second number of bits. An extrinsic information input to the ECC decoder is determined based at least in part on the first loop-back signal, the represented output of the signal detector, and at least one comparison with at least one predetermined threshold.