Multi-CPU Turbo Frequency Segmentation for Execution Jitter Reduction
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Solution Overview
Problem
Software applications running on multi-core processors experience execution jitter due to non-deterministic code execution timing, which is undesirable for applications requiring precise and predictable execution times, such as real-time and financial trading applications.
Innovation Solution
The system optimizes workload by allowing multiple CPUs to operate at distinct turbo frequencies, with the control circuit managing core configurations to reduce execution jitter by enabling a different number of cores on each CPU to operate at specific frequencies, using a turbo boost frequency table to select optimal frequencies and schedule AVX threads appropriately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple cores operate at the same turbo frequency, then processing speed is improved, but execution timing becomes non-deterministic causing jitter
Solution Approach 1:
The patent applies local quality by assigning different turbo frequencies to different CPU cores based on their specific workload characteristics. Frequency-sensitive threads are assigned to cores operating at one turbo frequency, while parallel execution-sensitive threads are assigned to cores operating at a different turbo frequency. This localized frequency assignment allows each core to be optimized for its specific thread type, maintaining both high processing speed and deterministic execution timing.
Solution Approach 2:
The patent segments the multi-core processor into distinct frequency zones, dividing cores into groups that operate at different turbo frequencies. This segmentation enables independent frequency control for different thread types, allowing the system to maintain deterministic execution timing for frequency-sensitive threads while still providing high-speed processing for parallel threads through separate frequency domains.
2Productivity
If all cores are enabled to maximize processing capacity, then productivity is improved, but execution jitter increases due to frequency sensitivity
Solution Approach 1:
The patent enables all cores to operate simultaneously but applies local quality by assigning different turbo frequencies to different core groups based on thread type. Frequency-sensitive threads are assigned to cores at a first turbo frequency, while parallel execution-sensitive threads are assigned to cores at a second turbo frequency. This allows maximum processing capacity utilization while maintaining execution timing consistency within each frequency group.
Solution Approach 2:
The patent segments the enabled cores into distinct frequency groups, allowing all cores to be productive while reducing jitter through frequency-based separation. Each segment operates at a predetermined turbo frequency selected to minimize execution jitter for its specific thread type, thereby maintaining both high productivity and timing consistency.
3Device complexity
If cores are disabled to reduce complexity, then device complexity is reduced, but processing speed decreases
Solution Approach 1:
The patent implements dynamic core management where the number of enabled cores and their turbo frequencies are adjusted based on the specific thread workload and execution requirements. The system dynamically selects which cores to enable and at what turbo frequency to operate them, optimizing the balance between processing speed and execution determinism without requiring static core disabling.
Solution Approach 2:
The patent changes operational parameters (turbo frequency and core enablement state) based on thread characteristics and execution requirements. Rather than permanently disabling cores, the system adjusts frequency parameters and core activation states dynamically to achieve deterministic execution timing while maintaining high processing speed when needed.
Data Source
AI summary
Systems and methods for a workload optimized server for intelligent algorithm trading platforms. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a control circuit coupled to the plurality of CPUs, the control circuit having a memory configured to store program instructions that, upon execution by the control logic, cause the IHS to: set a first number of enabled cores in a first CPU to operate with a first all-core turbo frequency, and set a second number of enabled cores in a second CPU to operate with a second all-core turbo frequency, where the first number of enabled cores is different from the second number of enabled cores, and where at least one of the first or second all core turbo frequencies is selected to cause the IHS to operate with reduced execution jitter.