Turbo Encoder Interleaver Index Generation Without Multipliers
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Solution Overview
Problem
Conventional turbo encoder interleaver index generation methods are inefficient, requiring multipliers and dividers, and increase processing time with input data size, leading to performance deterioration.
Innovation Solution
An apparatus and method that calculate interleaver indexes in parallel using a main processor and index operator, employing modular operations and multiplexers to derive indexes for multiple bits without the need for multipliers and dividers, utilizing equations like Π(i+1) - Π(i) = (f1 + f2 + 2*f2*i) mod K and Π(i+j+16) = 2*Π(i+j+8) - Π(i+j) + 128*f2 mod K.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional sequential index generation method is used, then hardware resources are simplified, but processing time increases and performance deteriorates
Solution Approach 1:
The patent segments the index generation process into two distinct parts: a main processor that calculates indexes for predetermined bits using the quadratic permutation polynomial formula, and index operators that calculate indexes for remaining bits in parallel using the segmented formula Π(i+j*8) = Π(i+(j-1)*8+8) + 128*f2 mod K. This segmentation enables parallel processing while maintaining accuracy.
Solution Approach 2:
The patent transitions from sequential single-bit index generation to parallel multi-bit index generation by introducing a new dimension of processing. The index operator uses the segmented formula to generate multiple indexes simultaneously by varying the parameter j, effectively moving from one-dimensional sequential processing to two-dimensional parallel processing.
2Measurement precision
If multipliers and dividers are used for index generation, then calculation accuracy is maintained, but hardware complexity and resource consumption increase
Solution Approach 1:
The patent replaces expensive, complex hardware components (multipliers and dividers) with simpler, more resource-efficient components (adders and modular arithmetic units). The index operator uses only addition and modular operations to generate indexes, eliminating the need for resource-intensive multiplication and division hardware while maintaining calculation accuracy.
Solution Approach 2:
The patent changes the computational parameters from requiring full multiplication and division operations to using segmented addition and modular arithmetic. By reformulating the index generation using Π(i+j*8) = Π(i+(j-1)*8+8) + 128*f2 mod K, the system achieves the same mathematical result with simpler operational parameters that require less hardware complexity.
3Productivity
If parallel index generation is implemented, then processing speed improves, but hardware resource requirements increase
Solution Approach 1:
The patent merges the functions of multiple index generators into a single integrated system. The main processor and index operators work together as a unified parallel processing architecture, where the index operator reuses the same computational units (adders and modular arithmetic circuits) to generate multiple indexes simultaneously, rather than requiring separate dedicated hardware for each index calculation.
Data Source
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AI summary
Disclosed is an apparatus and a method for generating an internal interleaver index of a turbo encoder in parallel. There are effects of reducing the time spent for generating total indexes by generating indexes for a plurality of bits in parallel and improving the resource efficiency and the performance in the hardware implementation by calculating indexes for following bits through the use of an index calculated for a predetermined bit without the use of a multiplier and a divider.