Turbo Interleaver Sizing for Contention-Free Parallel Decoding
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Solution Overview
Problem
Existing turbo coding systems face challenges in implementing contention-free interleavers for various information block sizes, leading to inefficiencies and potential memory access contentions during decoding, which affect the performance and scalability of communication systems.
Innovation Solution
A method for selecting interleaver sizes using a set of sizes defined by K″=ap×f, where a and f are integers, and adjusting sizes to avoid multiples of (2m−1, with the use of a permutation π(i)=(iP0+A+d(i))mod K′ for interleaving, ensuring contention-free and quasi-cyclic properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a turbo interleaver is designed to provide good weight distribution and error-correcting capabilities, then decoding performance is improved, but memory access contentions occur during parallel processing
Solution Approach 1:
The patent applies parameter changes by modifying the interleaver size to specific values that are multiples of the parallel processing factor. This allows the interleaver to be evenly divided into processing units, eliminating memory access contentions while preserving error-correcting capabilities through maintained weight distribution properties
Solution Approach 2:
The patent segments the interleaver into multiple independent processing units by designing the interleaver size as a multiple of the parallel processing factor. Each unit can process data independently without memory access conflicts, enabling efficient parallel decoding while maintaining overall code performance
2Ease of manufacture
If the interleaver size is fixed for a given information block size, then implementation is simplified, but scalability to different block sizes is reduced
Solution Approach 1:
The patent creates a universal interleaver design where the size is determined by a formula involving a base value and a parallel processing factor. This single design can be scaled to support multiple information block sizes by adjusting the base value, providing both implementation simplicity and scalability across different system requirements
3Productivity
If parallel processing is increased to improve decoding speed, then productivity is improved, but memory access contentions increase
Solution Approach 1:
The patent resolves the contradiction between parallel processing and memory access contentions by changing the interleaver size parameter to be a multiple of the parallel processing factor. This ensures that each processing unit has dedicated memory access patterns, allowing high-speed parallel decoding without contentions
Data Source
AI summary
A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K′ is determined that is related to K″, where K″ from a set of sizes; wherein the set of sizes comprise K″=ap×f, pmin≦p≦pmax; fmin≦f≦fmax, wherein a is an integer and f is a continuous integer between fmin and fmax, p takes integer values between pmin and pmax, a>1, pmax>pmin, pmin>1. The information block of size K is padded into an input block of size K′ using filler bits, if needed. Encoding is performed using the original input block and the interleaved input block to obtain a codeword block using a turbo encoder. The codeword block is transmitted through the channel.