Turbo LDPC Decoder Permutation Layout for Lower Interconnect Complexity
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Solution Overview
Problem
Low-density parity-check (LDPC) decoding is computationally complex, leading to increased memory requirements and interconnection complexity, which hinders efficient processing in systems like 60 GHz millimeter wave systems.
Innovation Solution
An iterative LDPC decoding system with a shift-register means for storing bit estimates, a parity-check processing means for generating messages, a combining means for updating bit estimates, and a fixed permutation means for facilitating storage and access, along with a second shift-register means for storing messages and subtracting earlier messages from updated bit estimates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative LDPC decoding procedures are used to improve decoding accuracy, then decoding reliability is improved, but computational complexity increases
Solution Approach 1:
The parity-check matrix is divided into multiple sub-matrices, and the decoding process is segmented into multiple stages corresponding to different sub-matrices. Each stage processes a portion of the code, breaking down the complex iterative decoding into manageable segments that can be executed with reduced computational overhead at each step.
Solution Approach 2:
The decoding process employs periodic action through multiple stages, where each stage performs a specific set of operations on the received signal before passing results to the next stage. This periodic processing structure allows the system to achieve reliable decoding while managing computational complexity through structured, repeated operations.
2Device complexity
If computational complexity is reduced to simplify processing, then device complexity is reduced, but memory requirements increase
Solution Approach 1:
By segmenting the decoding process into multiple stages with distinct functions, intermediate results can be processed and discarded in a structured manner. Each stage maintains only the memory required for its specific operations, reducing peak memory requirements compared to a monolithic decoding approach.
Solution Approach 2:
The system performs preliminary actions in each decoding stage by pre-processing the received signal and preparing intermediate results before the main decoding operations. This allows for more efficient memory utilization by preparing data in advance and processing it in organized batches, reducing the need for large intermediate storage.
3Reliability
If more processing stages are added to improve decoding performance, then decoding accuracy is improved, but interconnection complexity increases
Solution Approach 1:
The multiple processing stages are segmented into modular units with well-defined interfaces. Each stage processes specific portions of the data and passes results to the next stage through standardized connections, reducing the overall interconnection complexity compared to a fully interconnected multi-stage system.
Data Source
AI summary
An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.