Turbo Mode Control Algorithm for Processor Power Efficiency

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Solution Overview

Problem

Modern operating systems often disable turbo mode at low utilization levels to conserve power, leading to performance losses in single-threaded applications, as they enter turbo mode too frequently, causing inefficiencies and failing to provide performance benefits.

Innovation Solution

Implementing an intelligent turbo mode control algorithm that monitors C0 and P0 residency to determine when to enable turbo mode, using weighted counters to adjust utilization thresholds and filter non-turbo mode requests, allowing turbo mode to be activated only at high utilization levels, thereby optimizing power efficiency and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If turbo mode is enabled at low utilization levels, then performance benefits are provided, but power consumption increases excessively

Engineering Contradiction:

ImproveperformanceVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the utilization threshold parameter from a fixed value (80%) to a dynamic value that adapts based on thread count and workload characteristics. This allows the system to enter turbo mode at lower thresholds when thread count is high (amortizing power cost across multiple threads) while maintaining higher thresholds when thread count is low, thus optimizing the performance-power consumption tradeoff

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements dynamic adjustment of turbo mode entry thresholds based on real-time system state (thread count, workload type). The threshold is not static but adapts dynamically to current utilization conditions, allowing optimal performance-power balance across varying workloads and thread configurations

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If turbo mode is disabled in balanced mode, then power efficiency is improved, but performance benefits are lost

Engineering Contradiction:

Improvepower efficiencyVSAvoidperformance

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent modifies the utilization threshold parameter dynamically based on thread count, allowing turbo mode to be enabled at lower thresholds when multiple threads are present. This resolves the contradiction by making turbo availability conditional on system state rather than universally disabled, thus preserving performance benefits while maintaining power efficiency in single-threaded scenarios

Inventive Principle:

Principle #35Parameter changes

3Use of energy by moving object

If intelligent turbo delays entry for programmed delay, then power efficiency is improved, but responsiveness and single-threaded performance are reduced

Engineering Contradiction:

Improvepower efficiencyVSAvoidresponsiveness

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent implements dynamic threshold adjustment based on thread count rather than using a fixed time delay. This allows immediate turbo mode entry when thread count justifies it (maintaining responsiveness) while preventing premature entry when thread count is low (maintaining power efficiency), thus resolving the contradiction between power efficiency and responsiveness

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8904205B2Increasing power efficiency of turbo mode operation in a processor

Publication Date: 2014.12.02 INTEL CORP

AI summary

In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.