Turbo Program Mode Memory Write Speed Reliability

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Solution Overview

Problem

Current memory systems face challenges in achieving faster write speeds while maintaining reliability, particularly in meeting the increasing quality of service requirements for data storage and communication.

Innovation Solution

The implementation of a memory system with a memory device and controller that utilizes a turbo program mode to adjust the number of incremental step pulse program (ISPP) pulses for writing data, differing between a first memory block with fewer data bits and a second memory block with more data bits, and migrates data based on access frequency and maintenance time, optimizing write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of program pulses is increased to improve write reliability, then data retention is improved, but write speed decreases

Engineering Contradiction:
Improvewrite reliabilityVSAvoidwrite speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements a dynamic turbo program mode that adjusts the number of program pulses based on real-time conditions. The mode can be set or reset by the memory controller, allowing the system to dynamically switch between fast programming (fewer pulses) and reliable programming (more pulses) depending on the specific write operation requirements, thereby resolving the contradiction between speed and reliability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of program pulse count by introducing the turbo program mode. When the turbo program mode is set, the memory device applies a reduced number of program pulses (first number of program pulses) compared to the normal mode, enabling faster write operations while maintaining acceptable reliability for applications that prioritize speed

Inventive Principle:
Principle #35Parameter changes

2Reliability

If data is migrated frequently to maintain data integrity, then reliability is improved, but system performance and productivity decrease

Engineering Contradiction:
Improvedata integrityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing data migration proactively during idle states before data corruption occurs. The memory device monitors maintenance time and migrates data from the first memory block to the second memory block in advance, ensuring data integrity is maintained while minimizing the impact on system performance by utilizing otherwise wasted idle time

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory device performs self-service by automatically managing data migration during its idle states without requiring external intervention. The system monitors its own maintenance time requirements and autonomously migrates data to preserve integrity, thereby maintaining reliability while avoiding the performance penalty of scheduled migrations

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11532360B2Memory system, memory device, and method for operating memory device
Publication Date: 2022.12.20 SK HYNIX INC
  • US11532360B2 patent drawing
  • US11532360B2 patent drawing
  • US11532360B2 patent drawing

AI summary

When programming data in a first memory cell in a first memory block in a turbo program mode, the memory device may apply a first number of program pulses to the first memory cell, the first number of program pulses being smaller than the number of program pulses applied to the first memory cell when data is written to the first memory cell when the turbo program mode is reset. When migrating the data written to the first memory cell to a second memory cell in a second memory block, the memory device may apply a second number of program pulses to the second memory cell, the second number of program pulses being larger than the first number of program pulses.