Turbo Write Buffer Host Controller Meta Data Management
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in managing meta data storage and write operations, particularly in high-speed storage systems like UFS devices, where hardware-based host controllers are not fully utilized, leading to performance overhead and suboptimal write modes.
Innovation Solution
A memory system that employs a turbo write buffer at the host to manage meta data, utilizing a turbo write function that enables high-speed write operations by preferentially writing data to a single-level cell buffer and later migrating it to a multi-level cell storage, optimizing performance through a combination of SLC and TLC memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If software-based UFS driver is used to implement HPB features, then meta data management is achievable, but system overhead increases and performance decreases
Solution Approach 1:
The patent replaces the software-based meta data management mechanism with a hardware-based implementation. Specifically, the host controller includes a turbo write buffer and meta data buffer that operate in hardware to manage write operations and meta data, eliminating the overhead of software-based processing while maintaining full HPB functionality.
Solution Approach 2:
The patent introduces a hardware intermediary layer (the host controller with dedicated buffers) that sits between the host and storage device. This intermediary handles meta data management and write operations in hardware, reducing the burden on the software driver and improving overall system performance while maintaining ease of operation.
2Productivity
If conventional write operations are used without turbo write buffer, then device complexity is low, but write performance is insufficient for high-speed storage systems
Solution Approach 1:
The patent segments the write operation into two distinct phases: a fast write phase where data is initially written to the turbo write buffer in hardware, and a subsequent migration phase where data is moved to the main storage medium. This segmentation allows the high-performance phase to operate independently in hardware while the slower phase handles bulk storage, thereby improving write performance without proportionally increasing overall complexity.
Solution Approach 2:
The patent performs preliminary write operations to the turbo write buffer before finalizing storage in the main medium. This preliminary action allows data to be quickly staged in a high-speed buffer, improving write performance by decoupling the initial write speed from the final storage speed, while the buffer manages the complexity of coordination.
3Quantity of substance
If meta data is stored in the same buffer as data, then buffer utilization is maximized, but meta data management efficiency decreases
Solution Approach 1:
The patent physically separates the buffer into two distinct segments: a data buffer for storing user data and a dedicated meta data buffer for storing mapping information. This segmentation allows each buffer to be optimized for its specific purpose, improving meta data management efficiency by enabling independent access and management of meta data without interfering with data operations.
Solution Approach 2:
The patent introduces a dedicated meta data buffer as an intermediary structure that sits between the data buffer and the control logic. This intermediary allows efficient management of mapping information separate from data operations, enabling the controller to quickly access and update meta data without blocking data write operations, thereby improving overall management efficiency.
Data Source
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AI summary
A memory system includes a storage device including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device, and a host that accesses the storage device. The storage device transfers map data, in which a physical address of the nonvolatile memory device and a logical address provided from the host are mapped, to the host depending on a request of the host. The host stores and manages the transferred map data as map cache data. The map cache data are managed depending on a priority that is determined based on a corresponding area of the nonvolatile memory device.