Turbo Write Buffer Segmentation for NAND Storage Reliability
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Solution Overview
Problem
Current storage devices face challenges in achieving improved reliability and reduced costs while maintaining high write performance, particularly in managing data between different memory tiers in a multi-tier NAND memory system.
Innovation Solution
The implementation of a turbo write function that utilizes a turbo write buffer with single-level cell (SLC) technology for enhanced write performance, which can be configured in various modes to optimize storage capacity and reliability, and includes a mechanism to flush data from the turbo write buffer to a triple-level cell (TLC) user storage area based on internal policies or explicit commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-tier NAND memory system is used to reduce costs, then storage capacity and cost-effectiveness are improved, but write performance deteriorates due to the slower write speed of TLC compared to SLC
Solution Approach 1:
The storage device is segmented into multiple tiers with different memory cell types (SLC, MLC, TLC, QLC) organized in a hierarchical structure. Each tier serves a specific function: higher tiers (SLC) provide fast write performance for buffering, while lower tiers (TLC, QLC) provide high capacity and cost-effectiveness. This segmentation allows the system to achieve both high write performance and cost reduction by directing different types of data to appropriate tiers.
Solution Approach 2:
The controller acts as an intermediary that manages data movement between different memory tiers. It implements tiering policies that determine when and how data is migrated between tiers based on factors such as write performance requirements, storage capacity needs, and data access patterns. This intermediary management enables the system to dynamically balance between write performance and cost-effectiveness.
2Productivity
If SLC buffer is used to improve write performance, then write speed is improved, but storage capacity is reduced due to the higher cost and lower density of SLC compared to TLC
Solution Approach 1:
The buffer capacity allocated to SLC is made dynamic rather than fixed. The controller adjusts the amount of data retained in the SLC buffer based on current write performance requirements, data access patterns, and the availability of lower-tier storage capacity. This dynamic adjustment allows the system to optimize write speed when needed while maximizing storage capacity utilization when high-speed writing is not critical.
Solution Approach 2:
The system changes operational parameters such as buffer size allocation, tiering policies, and data migration thresholds to balance write speed and storage capacity. By adjusting these parameters dynamically based on system conditions, the device can achieve high write performance when necessary while maintaining efficient use of total storage capacity across all tiers.
Data Source
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Figure 3A~3B
Figure 4A
AI summary
A storage device includes a nonvolatile memory device including a first region and a second region, and a controller that receives a first operation command including move attribute information and a first logical block address from an external host device and moves first data corresponding from the first region to the second region in response to the received first operation command, and when the first operation command does not include the move attribute information, the controller performs a first operation corresponding to the first operation command.