Turret Handler Parallel Testing for Semiconductor Production Rate

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Solution Overview

Problem

Conventional semiconductor component testing processes are inefficient, leading to increased production costs and reduced production rates due to lengthy testing times and limited tester utilization, especially as semiconductor complexity increases.

Innovation Solution

A turret handler system with multiple independent turrets and test pads allows for simultaneous testing and transportation of semiconductor components, optimizing tester utilization by alternating testing between inner and outer turrets, thereby reducing overall testing time and increasing production efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional testing processes are used with single turret handlers, then the testing can be performed sequentially, but the production rate decreases and cycle time increases due to limited tester utilization

Engineering Contradiction:
Improveproduction rateVSAvoidcycle time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system divides the testing process into multiple parallel segments by introducing a main turret and multiple secondary turrets (first, second, and optionally third secondary turrets). Each turret can independently hold and transport semiconductor components to different test pads, enabling simultaneous testing of multiple components across multiple test pads connected to a single tester node.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system ensures continuous utilization of the tester by coordinating multiple turrets to alternately present components for testing. While one turret is transporting components or another is being loaded, the tester remains continuously engaged with at least one component, eliminating idle time and maximizing tester productivity throughout the entire cycle.

Inventive Principle:
Principle #20Continuity of useful action

2Productivity

If multiple test pads are used with a single tester, then more components can be tested simultaneously, but the device complexity increases

Engineering Contradiction:
Improvetester utilizationVSAvoidturret handler complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple secondary turrets share common functionality: each turret is equipped with pickup heads for holding components, transport mechanisms for moving components to test pads, and can be independently controlled. This multi-functional design allows the system to handle multiple components through identical operational sequences, simplifying control logic while increasing capacity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The main turret acts as an intermediary that receives components from component sources and distributes them to various secondary turrets. This intermediary structure simplifies the overall system architecture by creating a clear hierarchical flow: main turret → secondary turrets → test pads, reducing the complexity of direct coordination between multiple independent component sources and multiple test pads.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9594111B2Turret handlers and methods of operations thereof
Publication Date: 2017.03.14 INFINEON TECHNOLOGIES AG
  • US9594111B2 patent drawing
  • US9594111B2 patent drawing
  • US9594111B2 patent drawing

AI summary

In one embodiment, a method of testing a semiconductor component includes loading a plurality of semiconductor components into a main turret of a turret handler, transporting the plurality of semiconductor components using the main turret to a test area, and splitting the plurality of semiconductor components into a first set and a second set. The method further includes testing a first semiconductor component in the first set at a first test pad using a tester while transporting a second semiconductor component in the second set to a second test pad and testing the second semiconductor component using the tester while transporting the first semiconductor component out of the first test pad. The first set and the second set are merged into the plurality of semiconductor components and the plurality of semiconductor components are transported away from the test area using the main turret.