Transient Voltage Suppressor Layout Using CPODE Insulation Features
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink in size, conventional transient voltage suppressor structures require complex implantation processes and large doping distances, limiting integration density and increasing processing costs.
Innovation Solution
Implementing a Continuous Poly on Diffusion Edge (CPODE) process to form insulation features between neighboring transistors, defining a transient voltage suppressor junction without extra implantation, allowing precise tuning of punch-through voltage through layout adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transient voltage suppressor structures are used, then voltage suppression function is achieved, but device complexity increases due to complex implantation processes
Solution Approach 1:
The patent extracts the implantation process from the transient voltage suppressor formation, using purely geometric definitions through CPODE features and doping region patterns to define the suppressor junctions, eliminating the need for separate implantation steps while maintaining the voltage suppression function
Solution Approach 2:
The CPODE insulation features serve multiple functions: they provide electrical insulation between adjacent transistors and simultaneously define the geometry of transient voltage suppressor junctions through their proximity to doping regions, combining isolation and TVS formation into a single structural element
2Reliability
If conventional transient voltage suppressor structures are used, then voltage suppression is achieved, but manufacturing cost increases due to additional implantation steps
Solution Approach 1:
The patent merges the TVS junction definition with the existing CPODE insulation feature formation and doping region patterning processes, so that the TVS structures are created as a byproduct of these necessary fabrication steps rather than requiring separate dedicated implantation processes
Solution Approach 2:
The CPODE insulation features and doping regions self-organize to form the transient voltage suppressor junctions through their geometric arrangement and interaction, eliminating the need for external implantation intervention and allowing the structure to define itself through the fabrication process
3Area of moving object
If minimum feature sizes are reduced to increase integration density, then more components fit in given area, but transient voltage suppressor formation becomes more difficult
Solution Approach 1:
The patent applies local geometric modifications to specific regions around doping features, where CPODE insulation features are strategically positioned and sized to create TVS junctions only where needed, allowing precise control of suppressor characteristics at local scales compatible with reduced minimum feature sizes
Solution Approach 2:
The patent uses vertical layering and three-dimensional positioning of CPODE features relative to doping regions to define TVS junction geometry, transitioning from two-dimensional planar definitions to three-dimensional spatial relationships that enable TVS formation at smaller feature dimensions
4Reliability
If conventional TVS structures are used, then voltage suppression works, but processing time increases due to extra implantation steps
Solution Approach 1:
The patent performs preliminary geometric definition of TVS junction locations through CPODE feature placement and doping region patterning before any implantation occurs, so that when implantation happens, the TVS structures are already defined and no additional implantation steps are needed, saving processing time
Data Source
AI summary
Semiconductor devices with insulation features and methods of fabrication are provided. A method includes forming a first source/drain feature and a second source/drain feature over a substrate, wherein the first source/drain feature and the second source/drain feature are separated by a gate structure; removing the gate structure to form a trench; forming an insulation feature in the trench; and forming a functional circuit over the substrate, wherein a shunt path parallel to the functional circuit is defined under the insulation feature and between the first source/drain feature and the second source/drain feature.