TVS Device Segmented Avalanche Diodes Low Capacitance
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Solution Overview
Problem
Conventional transient voltage suppression devices (TVS) with single avalanche diodes have high capacitance, which affects data integrity in high-speed interfaces and require additional diodes to reduce capacitance, leading to increased parasitic resistance and inductance due to metal bonding wires, compromising chip performance at high frequencies.
Innovation Solution
A transient voltage suppression device with a substrate of a second conductivity type, featuring multiple wells and doped regions, and a metal connecting-wire layer that reduces parasitic resistance and inductance by allowing direct current leakage through the front surface, enhancing ESD protection without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single avalanche diode is used in TVS, then ESD protection capability is improved, but capacitance increases which affects data integrity in high-speed interfaces
Solution Approach 1:
The patent segments the single avalanche diode into multiple parallel avalanche diodes (first avalanche diode and second avalanche diode) with different breakdown voltages. This segmentation allows the TVS device to maintain low capacitance while providing comprehensive ESD protection across different voltage levels, resolving the contradiction between protection capability and capacitance.
Solution Approach 2:
The patent changes the parameter of breakdown voltage by designing multiple avalanche diodes with different breakdown voltage parameters. The first avalanche diode has a first breakdown voltage and the second avalanche diode has a second breakdown voltage, allowing the device to handle different ESD scenarios while maintaining low overall capacitance.
2Manufacturing precision
If additional diodes are connected in series to reduce capacitance, then capacitance decreases, but parasitic resistance and inductance increase due to metal bonding wires
Solution Approach 1:
The patent merges multiple avalanche diodes in parallel configuration rather than series connection. This merging approach reduces capacitance while avoiding the need for additional metal bonding wires that would introduce parasitic resistance and inductance, thus resolving the contradiction between capacitance reduction and parasitic minimization.
Solution Approach 2:
The patent transitions from a series connection approach (one-dimensional arrangement requiring additional wires) to a parallel connection approach (multi-dimensional integration within the same chip area). This dimensional change allows capacitance reduction without introducing additional parasitic elements from bonding wires.
3Reliability
If metal bonding wires are used to connect electrodes, then ESD protection is achieved, but parasitic resistance and inductance increase compromising high-frequency performance
Solution Approach 1:
The patent extracts and eliminates the need for metal bonding wires by integrating the ESD protection function directly into the semiconductor chip structure through multiple parallel avalanche diodes. This extraction removes the source of parasitic resistance and inductance while maintaining ESD protection capability.
Solution Approach 2:
The patent introduces an intermediary structure where multiple avalanche diodes with different breakdown voltages serve as mediators between the input signal and ground, providing ESD protection without requiring external metal bonding wires. This intermediary approach resolves the contradiction by achieving protection through internal chip structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves the current capability for negative-impulse ESD and reduces the impact of parasitic resistance and inductance, ensuring reliable protection for high-speed interfaces while maintaining compact design.
Implementation Method 1
transient voltage suppressors (TVS), as a highly effective protection device with PN-junction, are widely used for various I/O interfaces due to their rapid response and high withstand against the ESD
Implementation Method 2
a metal connecting-wire layer including a first metal connecting-wire and a second metal connecting-wire and located on the substrate, the first metal connecting-wire being electrically connected to the first doped region and the sixth doped region as being used as a first potential terminal
Data Source
AI summary
A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.