TVS Well Structure for Low-Capacitance HDMI ESD Protection
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Solution Overview
Problem
High-speed interfaces, such as HDMI, require stringent ESD protection due to rapid voltage transients, which existing transient voltage suppressors (TVS) struggle to address effectively, especially in densely packed chip designs with hundreds of pins, leading to potential damage and data integrity issues.
Innovation Solution
A transient voltage suppression device is designed with a substrate of a second conductivity type, featuring multiple well regions and doped regions forming a silicon-controlled rectifier and diodes, which are integrated to provide robust ESD protection with reduced parasitic capacitance and increased current capability, avoiding parasitic BJT switch-on and enabling efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional TVS structures are used to protect I/O interfaces, then ESD protection capability is provided, but parasitic capacitance is high which affects high-speed signal integrity
Solution Approach 1:
The TVS device is segmented into multiple functional regions: a first breakdown region with first doped regions for Zener breakdown, a second breakdown region with second doped regions for avalanche breakdown, and a third breakdown region with third doped regions. This segmentation allows the device to achieve comprehensive ESD protection while controlling parasitic capacitance through distributed charge storage regions.
Solution Approach 2:
Different regions of the TVS device are doped with different conductivity types and concentrations to create localized functional properties. The first doped regions provide Zener breakdown characteristics, the second doped regions provide avalanche breakdown characteristics, and the third doped regions provide additional breakdown mechanisms. This local quality differentiation enables optimized ESD protection across different voltage ranges while minimizing overall parasitic capacitance.
2Reliability
If multiple TVS devices are integrated to protect hundreds of pins, then ESD protection coverage is improved, but chip area increases
Solution Approach 1:
Multiple TVS functions are merged into a single integrated device structure. The patent combines Zener diode functionality, avalanche diode functionality, and additional breakdown region functionality into one unified TVS device that can protect multiple I/O pins. This merging reduces the total chip area required compared to using separate TVS devices for each protection function.
Solution Approach 2:
The TVS device structure is designed to provide universal ESD protection across multiple I/O interfaces. The combination of first, second, and third breakdown regions creates a multi-functional device that can handle various ESD scenarios (different voltage levels, different pulse durations) that would otherwise require multiple specialized TVS devices, thereby reducing overall chip area.
3Reliability
If TVS devices are added to protect high-speed interfaces, then ESD robustness is improved, but response time and signal integrity may be affected
Solution Approach 1:
The TVS device utilizes dynamic breakdown mechanisms that activate only during ESD events. The first, second, and third breakdown regions remain in high-impedance state during normal operation, allowing high-speed signals to pass unaffected. During ESD events, the breakdown regions dynamically switch to low-impedance state to shunt the surge current, providing rapid response without affecting normal signal transmission speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively clamps input/output voltages within safe ranges, providing strong ESD robustness and reducing parasitic capacitance, thus protecting high-speed interfaces from damage while minimizing chip area and manufacturing costs.
Implementation Method 1
The first doped region is used as a cathode of a Zener diode, and the Zener diode well region is used as an anode of the Zener diode
Implementation Method 2
A transient voltage suppression device is provided, including a substrate being of a second conductivity type; a first conductivity type well region disposed in the substrate and including a first well, a second well, and a third well
Data Source
AI summary
A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.