Data Storage Device Tweak Buffer for Hidden Decryption Latency
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Solution Overview
Problem
The latency associated with tweak generation in AES-XTS decryption processes in data storage devices, particularly in MRAM Channel Controllers, contributes significantly to the overall read latency, necessitating a solution to hide this latency and reduce the total decryption latency.
Innovation Solution
Implementing a tweak buffer in the decryption engine, where the tweak value is calculated and stored during the logical-to-physical address translation process, allowing parallel processing with data retrieval, thereby hiding the tweak generation latency within the read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential tweak generation and data decryption is used, then decryption accuracy is maintained, but total decryption latency increases
Solution Approach 1:
The tweak value is calculated in advance during the address translation process before data decryption is needed. The translation engine computes the tweak value from the logical address and stores it in a buffer, so that when decryption occurs, the tweak value is already ready, eliminating sequential waiting time.
Solution Approach 2:
The decryption process is divided into independent segments: address translation, tweak value generation, and data decryption. These segments are executed in parallel by different engines (translation engine vs. decryption engine), allowing the tweak generation to occur independently before the actual decryption operation.
2Loss of time
If parallel tweak generation and data retrieval are implemented, then decryption latency is reduced, but buffer management complexity increases
Solution Approach 1:
A buffer is introduced as an intermediary component between the translation engine and decryption engine. This buffer stores the generated tweak values temporarily, allowing the translation engine to produce tweak values independently and make them available to the decryption engine without direct complex coordination or synchronization between the two engines.
3Loss of time
If tweak value is calculated during address translation, then latency is hidden within translation time, but translation process becomes more complex
Solution Approach 1:
The tweak value generation function is merged with the address translation process. The translation engine, which already performs logical-to-physical address translation, also computes the tweak value from the logical address using the same key material, combining two operations into one unified process that executes in parallel.
Data Source
AI summary
A decryption engine can decrypt encrypted data read from a physical address in a memory of a data storage device. To decrypt the data, the decryption engine can use a tweak value that is generated from a logical address associated with the physical address. To reduce latency, the tweak value can be generated in parallel with the translation of the logical address to the physical address. The tweak value can be stored in a tweak buffer in the decryption engine until needed and can be indexed by a tag associated with a process in a host that is requesting the data. The tweak buffer can use static random-access memory (SRAM) or a content-addressable memory (CAM), for example. Other embodiments are provided.