Twin Bit Cell Silicon Nitride Insert Undercut Gate
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Solution Overview
Problem
Conventional methods for manufacturing twin-bit cell structures in flash memory devices face challenges in scaling down due to difficulties in controlling gates independently and forming insulating regions, limiting further miniaturization and increasing circuit density.
Innovation Solution
A method involving the formation of undercut regions in a polysilicon gate structure, followed by the deposition of silicon nitride material and selective etching to create insert regions, which allows for self-aligned etching processes and increased device scaling without the need for lithographic alignment, enabling the formation of high-density twin-bit cell structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used for twin-bit cell structures, then manufacturing process is simpler, but device scaling is limited due to difficulties in controlling gates independently and forming insulating regions
Solution Approach 1:
The patent divides the gate structure into two independently controllable gates (first gate and second gate) within the twin-bit cell structure. Each gate can be independently controlled through separate control gates, allowing independent programming and erasing operations. This segmentation enables finer device scaling while maintaining controllability.
Solution Approach 2:
The patent introduces a vertical dimension by forming insulating regions (silicon oxide layers) underneath the gate structure at different depths. The first insulating region is formed at a first depth and the second insulating region at a second depth, creating a three-dimensional arrangement that enables independent gate control and overcomes planar scaling limitations.
2Productivity
If conventional manufacturing methods are used, then process steps are fewer, but circuit density cannot be increased due to minimum feature size limitations
Solution Approach 1:
The patent transitions from two-dimensional planar scaling to three-dimensional structuring by forming insulating regions at different depths underneath the gate. This vertical arrangement allows continued circuit density improvement without being constrained by minimum lateral feature sizes, effectively adding a depth dimension to the manufacturing process.
Solution Approach 2:
The patent nests multiple functional regions within the twin-bit cell structure, including first and second charge trapping regions, first and second tunneling regions, and insulating regions at different depths. This nested arrangement maximizes the use of available space, enabling higher circuit density without increasing the lateral footprint of each cell.
3Volume of moving object
If twin-bit cell structure is scaled down, then device size decreases, but gate independent control becomes difficult to maintain
Solution Approach 1:
The patent uses vertical stacking of insulating regions at different depths to maintain electrical isolation between gates as device size decreases. The first insulating region at a first depth and the second insulating region at a second depth provide independent control paths, ensuring gate reliability even in scaled-down devices.
Solution Approach 2:
The patent introduces insulating regions (silicon oxide layers) as intermediary structures between the gates and the substrate. These intermediary regions provide electrical isolation and enable independent gate control by preventing unwanted coupling, even when the overall device dimensions are reduced.
4Manufacturing precision
If conventional manufacturing processes are used, then manufacturing cost is lower, but further miniaturization is limited
Solution Approach 1:
The patent adds a vertical dimension to the manufacturing process by forming insulating regions at different depths using sequential deposition and etching steps. This approach enables further miniaturization by utilizing the depth dimension rather than relying solely on lateral scaling, which is constrained by conventional process capabilities.
Solution Approach 2:
The patent performs preliminary actions by forming the first insulating region and first charge trapping region before forming the second insulating region and second charge trapping region. This sequential approach allows each layer to be optimized independently and simplifies the overall manufacturing process by breaking down the complex multi-layer structure into manageable fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable and cost-effective manufacturing of twin-bit cell structures, allowing for further scaling down of device sizes and increased circuit density without reducing the critical dimensions of the silicon wafer, thereby enhancing memory device performance and efficiency.
Implementation Method 1
exposes the ensemble of the semiconductor substrate including the polysilicon gate structure and the gate dielectric layer having the undercut region to an oxidizing environment to cause a formation of a first silicon oxide layer overlying a peripheral surface of the gate polysilicon structure and a second silicon oxide layer overlying a portion of the surface of the semiconductor substrate
Data Source
AI summary
A method for manufacturing a twin bit cell structure with a silicon nitride material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, a silicon nitride material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The silicon nitride material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed silicon nitride material and the polysilicon gate structure.