Twin-Bit RRAM Resistor Structure for Via Misalignment Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device layouts face challenges in achieving precise resistance matching between resistive random access memory (RRAM) resistors due to misalignment of conductive vias, leading to inconsistent resistance values and operational issues.
Innovation Solution
The integration of a twin bit RRAM resistor device structure, where conductive features and resistive material layers are strategically aligned and electrically coupled to ensure resistance matching, even in cases of via misalignment, by forming conductive features at different horizontal levels and using resistive material layers to surround conductive vias, thereby stabilizing resistance across devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-bit RRAM resistor structure is used, then device simplicity is maintained, but resistance matching precision deteriorates due to via misalignment
Solution Approach 1:
The RRAM resistor device is divided into two independent bits (first bit and second bit), each with its own resistive material layer and electrode structure. This segmentation allows each bit to be independently controlled and measured, enabling precise resistance matching between the two bits even when via misalignment occurs during manufacturing.
Solution Approach 2:
The patent transitions from a conventional single-bit planar structure to a three-dimensional stacked structure with multiple horizontal levels. The first and second resistive material layers are positioned at different vertical levels, with conductive features connecting them through vias. This dimensional change allows for better alignment tolerance and resistance matching by distributing the electrical path across multiple levels.
2Ease of manufacture
If conductive via alignment is relaxed for easier manufacturing, then manufacturing complexity is reduced, but resistance value consistency deteriorates
Solution Approach 1:
The patent applies different structural configurations to different local regions of the device. The first bit and second bit have locally optimized electrode and resistive material layer arrangements that compensate for potential via misalignment. Each bit's local structure is designed to maintain consistent resistance characteristics despite variations in via positioning.
Solution Approach 2:
The dual-bit stacked structure inherently provides a cushioning effect against via misalignment. By having redundant conductive paths and distributed electrical connections across multiple levels, the structure pre-compensates for potential alignment errors, ensuring that resistance values remain consistent even when via positioning varies within acceptable tolerances.
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.