Twin-Bit Trench Floating-Gate Memory Cells for Higher Density
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Solution Overview
Problem
Current non-volatile memory devices face challenges in reducing the size of memory cells to increase density on a semiconductor substrate surface area, as existing configurations require significant space for channel regions and floating gates.
Innovation Solution
The development of a twin bit memory cell design featuring two separate trenches on the substrate surface with a single floating gate in each trench, eliminating the need for a separate drain region and utilizing a continuous channel region extending from one source region to another, allowing for miniaturization and efficient programming and erasure of data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar memory cell configuration is used with separate source and drain regions, then the channel region can be formed at the surface, but the memory cell occupies larger substrate surface area
Solution Approach 1:
The patent merges the source and drain regions into a single shared source region for both memory cells in the trench, eliminating the need for separate drain regions. This consolidation reduces the overall substrate surface area occupied by the memory cell structure while maintaining the necessary channel regions for operation.
Solution Approach 2:
The patent transitions from a planar surface configuration to a three-dimensional trench structure, forming channel regions that extend along the sidewalls of the trench. This vertical dimensionality change allows the memory cells to be packed more densely on the substrate surface, reducing the horizontal area occupied by each cell.
2Productivity
If trenches are formed into the substrate surface to increase memory cell density, then more memory cells can be formed per unit area, but the channel region becomes non-linear and extends along the trench sidewall
Solution Approach 1:
The patent utilizes the vertical dimension by forming trenches into the substrate and creating channel regions that extend along the trench sidewalls. This three-dimensional configuration increases the number of memory cells that can be formed per unit substrate area by effectively using the vertical space within the trench structure.
Solution Approach 2:
The patent segments the channel region into distinct portions: a first portion extending along the first trench sidewall, a second portion extending along the substrate surface between trenches, and a third portion extending along the second trench sidewall. This segmentation allows the channel to navigate the complex three-dimensional geometry while maintaining functional integrity.
3Area of stationary object
If floating gates are buried in trenches to reduce surface area, then memory cell size is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent forms floating gates within the three-dimensional trench structure rather than on the planar surface. This vertical placement within the trench reduces the horizontal footprint of the memory cell while the floating gates remain accessible through the trench opening for programming and erasure operations.
Solution Approach 2:
The patent employs a single shared source region that serves both memory cells in the trench, and uses the same floating gate structure for both storing data and controlling the channel conduction. This multi-functionality reduces the total number of components needed, offsetting the increased manufacturing complexity of the trench structure.
4Length of moving object
If a continuous channel region extends from one source region to another through trenches, then miniaturization is achieved, but the channel region must navigate complex three-dimensional paths
Solution Approach 1:
The patent divides the continuous channel region into distinct segments: a first portion along the first trench sidewall, a second portion across the substrate surface, and a third portion along the second trench sidewall. This segmentation allows each portion to be optimized for its specific geometric constraints while maintaining overall continuity for carrier transport.
Solution Approach 2:
The channel region utilizes three-dimensional space by extending along trench sidewalls and across the substrate surface in different spatial planes. This multi-planar configuration allows the channel to connect source and drain regions while accommodating the miniaturized trench-based memory cell structure.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.