Twin Cell Masking Circuit for Erasure Verification

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor nonvolatile memory devices, there is a risk that the data written before erasure may still be read after the erasure process, leading to potential security issues due to the possibility that the threshold voltage relationship between memory cells remains unchanged post-erasure.

Innovation Solution

A semiconductor device is designed to mask data when the threshold voltages of both storage elements in a twin cell are lower than the erasure determination level, preventing the reading of pre-erased data by outputting a fixed or random value instead of the actual data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If erasure operation is performed to lower threshold voltages of both memory cells, then data is intended to be erased, but the magnitude relation between threshold voltages may be maintained resulting in data leakage

Engineering Contradiction:
Improvedata securityVSAvoidincomplete data erasure
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent applies preliminary action by performing a verification read operation after erasure to check whether the threshold voltage relationship has been properly reset. Before considering the erasure complete, the system reads the twin cell again to verify that both cells now show low threshold voltage characteristics, ensuring that no residual data relationship remains that could allow data recovery.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the read operation results to determine whether erasure was successful. The sense circuit measures the threshold voltages of both cells, and this measurement feedback is used to verify that the erasure operation achieved the desired effect of eliminating the threshold voltage difference that encodes data.

Inventive Principle:
Principle #23Feedback

2Productivity

If threshold voltage relationship is not fully reset after erasure, then erasure operation appears complete, but data can still be read leading to security issues

Engineering Contradiction:
Improveerasure operation speedVSAvoiddata erasure completeness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs a preliminary verification read immediately after the erasure operation to ensure complete data destruction. This additional read step, while adding some time to the overall process, guarantees that the threshold voltage relationship has been properly reset before the system considers the erasure complete and allows the device to return to normal operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9558838B2Semiconductor device for masking data stored in twin cell and outputting masked data
Publication Date: 2017.01.31 RENESAS ELECTRONICS CORP
  • US9558838B2 patent drawing
  • US9558838B2 patent drawing
  • US9558838B2 patent drawing

AI summary

A memory array includes a plurality of twin cells, each of the twin cells composed of a first storage element and a second storage element configured to hold binary data according to a difference in threshold voltage between them, the first storage element and the second storage element each being electrically rewritable. Upon receiving a request to read the twin cell, when the threshold voltage of the first storage element forming the twin cell is lower than an erasure determination level and the threshold voltage of the second storage element forming the twin cell is lower than the erasure determination level, an output circuit masks the data stored in the twin cell and outputs the masked data.