Twin Cell PUF Structure for Multi-CRP Support
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Solution Overview
Problem
Conventional Physically Unclonable Functions (PUFs) are limited in supporting multiple challenge-response pairs (CRPs), requiring multiple instances of weak PUFs on a chip, which increases chip area and is inefficient for applications needing strong PUF capabilities.
Innovation Solution
A strong twin cell memory-based PUF structure is developed, utilizing an array of twin cells divided into portions with interconnected bitlines and decoders to form bitcells from combinations of twin cells, enabling multiple CRPs with the same number of twin cells, and a method for operating this structure to generate unique bitstrings in response to challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple instances of weak PUF are used on the same chip to support multiple CRPs, then the number of supported CRPs increases, but the chip area consumption increases significantly
Solution Approach 1:
The patent merges multiple weak PUF instances into a single integrated structure by sharing common resources (bitlines, sense amplifiers, decoders) among multiple twin cell arrays. This allows multiple CRPs to be supported while significantly reducing the total chip area compared to implementing separate weak PUF instances.
Solution Approach 2:
The patent creates a multi-functional PUF structure where a single chip can support multiple CRPs through configurable twin cell arrays. The same hardware infrastructure (bitlines, sense amplifiers, column decoders) serves multiple CRP generation functions, enabling one chip to replace multiple weak PUF instances.
2Adaptability or versatility
If a strong PUF structure is implemented to support multiple CRPs, then the security and versatility improve, but the device complexity increases
Solution Approach 1:
The patent segments the PUF structure into modular twin cell arrays with systematic organization. Each twin cell array is divided into portions with specific bitline connections, creating a segmented but manageable structure that reduces overall complexity while maintaining strong PUF capabilities.
Solution Approach 2:
The patent introduces column decoders as intermediary components that manage the complexity of connecting twin cells to bitlines and sense amplifiers. These decoders act as mediators that simplify the control logic and make the system more manageable while enabling multiple CRP support.
3Device complexity
If read operations are directed to individual twin cells as in prior art, then the PUF structure is simple, but only a single CRP can be supported
Solution Approach 1:
The patent extends the read operation capability from a single dimension (individual twin cell) to multiple dimensions by enabling selective reading of different twin cell portions through different bitline connections. This dimensional expansion allows the same hardware to support multiple CRPs by varying the read configuration.
Solution Approach 2:
The patent introduces dynamic configurability to the read operations, where the column decoders can selectively connect different twin cell portions to bitlines based on the required CRP. This dynamic switching capability enables multiple CRPs to be supported without permanently increasing structural complexity.
Data Source
AI summary
A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.


