Twin-Channel Access Structure for Higher-Current 3D Memory Cells
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Solution Overview
Problem
As DRAM scaling becomes challenging in vertical three-dimensional (3D) memory architectures, there is a need for enhanced access current and capacitance while minimizing cell volume and footprint, with existing technologies facing difficulties in maintaining retention and scalability due to increased aspect ratios and variability across multiple tiers.
Innovation Solution
The implementation of a twin channel access device with two transistors and two storage nodes, which doubles the channel width and shares a storage node, allowing for improved access current and capacitance without increasing cell volume, and reduces the horizontal area footprint, thereby enhancing scalability and retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical three-dimensional memory architecture is used to increase storage density, then storage capacity is improved, but access current and capacitance are reduced
Solution Approach 1:
The access device is divided into two separate transistors (first access transistor and second access transistor) that operate independently to access different storage nodes. This segmentation allows each transistor to provide sufficient access current while collectively achieving higher storage capacity through multiple storage nodes per access device.
Solution Approach 2:
Multiple storage nodes (first storage node and second storage node) are combined and shared by the twin channel access device. This merging allows the access device to access multiple storage locations through two channels, effectively increasing the storage capacity accessible by a single access device while maintaining adequate access current through dual-transistor design.
2Quantity of substance
If cell volume is reduced to increase density, then storage density is improved, but retention is degraded
Solution Approach 1:
The patent transitions from planar memory architecture to vertical three-dimensional architecture by stacking multiple tiers vertically. This dimensional change allows storage nodes to be arranged in three dimensions rather than two, increasing storage density without proportionally reducing the volume available for each storage node, thereby maintaining retention characteristics.
Solution Approach 2:
The twin channel access device merges multiple access transistors and storage nodes into a compact unit cell structure. By sharing storage nodes between two access transistors and implementing dual-channel access, the design achieves higher storage density while each storage node maintains adequate size for proper retention through the combined capacitance of multiple nodes.
3Quantity of substance
If horizontal area footprint is reduced to increase density, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent moves from two-dimensional planar scaling to three-dimensional vertical stacking. This dimensional transition allows storage nodes to be arranged vertically across multiple tiers rather than horizontally in a single plane, increasing storage density without further reducing the already minimal horizontal footprint to the point where manufacturing alignment becomes prohibitively difficult.
Solution Approach 2:
The memory structure is segmented into multiple discrete tiers stacked vertically, with each tier containing storage nodes and access devices. This segmentation into modular tiers allows for more relaxed horizontal alignment requirements within each tier while achieving overall high density through the vertical stacking of multiple such modules.
Data Source
AI summary
Systems, methods and apparatus are provided for a twin channel access device, twin storage node memory cell in a vertical three-dimensional memory. The memory cell has a horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. The first channel is actuated by a first gate separated from the first channel region by a first gate dielectric. The access device further includes a third source/drain region and a fourth source/drain region separated by a second channel region. The second channel is actuated by a second gate separated from the second channel region by a second gate dielectric. The first and the second gate are connected. A horizontally oriented storage node is coupled to the second and/or fourth source/drain regions of the twin channel access device.