Twin-Drain Quantum Well FETs for Multi-Valued Logic Switching
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Solution Overview
Problem
Conventional Field-Effect Transistors (FETs) are limited to processing one bit of information at a time and are not capable of multi-valued logic, restricting their application in advanced logic circuits and memory devices.
Innovation Solution
The development of Spatial Wavefunction Switching (SWS) FETs with an asymmetric coupled quantum well structure, featuring two quantum wells of different thicknesses and energy gaps, and barrier layers, allowing for the routing of electrical signals between multiple drains and sources based on gate voltage, enabling multi-valued logic and enhanced memory retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FETs with single transport channel and single drain are used, then device structure is simple, but information processing capability is limited to one bit at a time
Solution Approach 1:
The transport channel is segmented into multiple quantum wells (first quantum well and second quantum well) that are spatially separated and electrically isolated from each other. Each quantum well can independently host charge carriers and be controlled by the gate, enabling parallel information processing across multiple channels while maintaining a unified device structure.
Solution Approach 2:
The patent transitions from a conventional single-channel FET to a multi-well structure where additional transport channels are created in the vertical dimension through quantum well formation. This dimensional expansion allows multiple bits of information to be processed simultaneously by utilizing the spatial separation of quantum wells at different depths within the semiconductor layer.
2Adaptability or versatility
If multiple quantum wells with different thicknesses and materials are used, then spatial wavefunction switching capability is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
Different quantum wells are designed with locally optimized properties - each quantum well has specific thickness and material composition tailored to its intended function. The first quantum well and second quantum well can have different thicknesses and material compositions to optimize carrier confinement and switching characteristics for each individual channel, rather than requiring all wells to have identical specifications.
Solution Approach 2:
The patent employs asymmetric quantum well structures where the first quantum well and second quantum well have deliberately different thicknesses and/or material compositions. This asymmetry creates distinct energy level structures and wavefunction distributions in each well, enabling controlled spatial switching of charge carriers between wells through gate voltage modulation while simplifying the manufacturing process by avoiding the need for perfectly symmetric structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
SWS FETs enable processing of multiple bits of information simultaneously, improving logic circuit performance and memory retention time, and reducing the number of FETs required for a given logic function, making them superior to conventional devices.
Implementation Method 1
the gate region is configured to control charge carrier location in a transport channel
Implementation Method 2
the transport channel includes an asymmetric coupled quantum well layer having at least two quantum wells... the at least two quantum wells including an upper well and a lower well... allowing for the switching of charge carriers between the wells based on gate voltage
Data Source
AI summary
A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.