Twin Memory Cell Interconnection Structure for Independent Bitline Reading
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Solution Overview
Problem
Conventional memory plane structures with twin memory cells require a negative reading inhibiting voltage to be applied to one twin memory cell when reading another, which complicates the reading process.
Innovation Solution
The memory plane structure is modified to include two bitlines per column, where adjacent twin memory cells are connected to different bitlines, allowing each memory cell to be read independently without applying a negative voltage to its twin, using conductive paths and vias through isolating layers to connect the bitlines to floating gate transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If twin memory cells share a common bitline, then space efficiency is improved, but reading complexity increases due to need for negative inhibiting voltage
Solution Approach 1:
The patent divides the bitline connection by assigning different bitlines to twin memory cells. Instead of sharing a common bitline, each twin cell (e.g., C1,j and C2,j) is connected to a separate bitline (B1,j and B2,j respectively), allowing independent reading operations without requiring inhibiting voltages on shared lines.
Solution Approach 2:
The patent introduces a new dimension in the interconnection structure by using multiple bitlines per column. The bitline architecture is extended from a single shared line to multiple independent lines, adding vertical and horizontal routing dimensions through vias and conductive paths in isolating layers to connect memory cells to their dedicated bitlines.
2Ease of manufacture
If twin memory cells are connected to the same bitline, then manufacturing simplicity is improved, but operational flexibility deteriorates
Solution Approach 1:
The patent segments the bitline connection architecture so that twin memory cells are no longer forced into a shared connection. Each cell can be independently routed to its own bitline through the isolating layers, enabling selective activation and independent operation of twin cells during read, program, and erase operations.
Solution Approach 2:
The interconnection structure is extended into additional dimensional space by routing bitlines through multiple isolating layers (I0, I1, I2, I3, I4) and using vias to establish vertical connections. This multi-layer approach provides routing flexibility and independent connectivity while maintaining planar integration.
3Measurement precision
If negative reading inhibiting voltage is applied to twin memory cell, then reading accuracy is improved, but device reliability deteriorates due to additional voltage stress
Solution Approach 1:
The patent extracts and eliminates the requirement for negative reading inhibiting voltage by providing dedicated bitline connections. The reading operation can proceed using only positive voltages on the selected memory cell's bitline and control gate, removing the harmful negative voltage stress that was previously necessary to prevent simultaneous reading of twin cells.
Data Source
AI summary
Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.