Twin Memory Cell Programming with Shared Select Gate
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Solution Overview
Problem
Conventional memory arrays with twin memory cells face challenges in optimizing operations such as reading and programming, particularly in terms of current consumption, due to unnecessary current flow in unprogrammed twin cells during programming and over-erased states leading to reading errors.
Innovation Solution
Implementing a method where the second memory cell in a pair is subjected to a soft programming voltage that prevents it from switching to a programmed state, using a positive voltage on its control gate line without applying a programming current, and applying zero voltage during reading to prevent over-erasure and reduce current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage control circuits are used for twin memory cells, then reading and programming operations can be performed, but current consumption increases and reading errors occur due to over-erased states
Solution Approach 1:
The patent applies different voltage parameters to the first and second control gate lines during programming operations. Specifically, a first voltage is applied to the first control gate line while a second voltage (different from the first) is applied to the second control gate line. This parameter differentiation prevents over-erasure of the non-selected memory cell while enabling programming of the selected cell, thereby improving reading accuracy and reducing current consumption without requiring complex control circuits
2Area of stationary object
If twin memory cells share a common select gate, then device footprint is reduced, but independent control of individual cells becomes more difficult
Solution Approach 1:
The patent segments the control mechanism by providing separate control gate lines (first control gate line and second control gate line) for each memory cell within the twin cell structure. Although the select gate is shared, the control gates are independently controllable, allowing selective programming or inhibition of individual cells. This segmentation enables independent cell control while maintaining the space-efficient shared select gate architecture
3Speed
If programming voltage is applied to one memory cell, then programming speed is improved, but the twin cell may enter an over-erased state causing reading errors
Solution Approach 1:
The patent applies a preliminary inhibiting voltage to the second control gate line before and during the programming operation on the first memory cell. This preliminary anti-action prevents the second memory cell from entering an over-erased state that would cause reading errors. By pre-establishing the protective voltage condition, the patent enables fast programming of the selected cell while protecting the non-selected cell from damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces current consumption during programming and reading operations, prevents over-erasure, and maintains accurate state detection by ensuring no memory cell has a negative threshold voltage, thus enhancing operational efficiency and reliability.
Implementation Method 1
Each memory cell is erased by combining the positive voltage applied to the substrate with a negative voltage applied to the control gate CG of its floating-gate transistor, while the control gate of the floating-gate transistor of the twin memory cell receives a positive erase-inhibit voltage preventing it from being simultaneously erased. Similarly, a memory cell is programmed by combining a negative voltage applied to the bit line BL and to the substrate PW with a positive voltage applied to the control gate CG of its floating-gate transistor
Implementation Method 2
programming the first memory cell by hot-electron injection, by means of a programming current passing through the first memory cell, by applying a first positive voltage to the bit line and a second positive voltage to the first control gate line
Data Source
AI summary
The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.