Twin-Well CMOS Display Driver Integration
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Solution Overview
Problem
Current wearable display devices, such as head-mounted displays, require high resolution and a large display area while minimizing non-display areas to prevent dizziness and enhance user experience.
Innovation Solution
A display device design that includes a pixel driver circuit, a scan driver with distinct transistor groups, and a display panel with a CMOS layer featuring well areas doped with different types of impurities, allowing for efficient placement of pixel transistors and scan transistors to reduce non-display areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution display specifications (2000 PPI) are implemented in wearable devices, then display quality and user comfort are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the pixel driver circuit and scan driver circuit onto the same semiconductor substrate within the display area. This integration eliminates the need for separate driver circuit substrates and reduces the number of connection interfaces, thereby reducing device complexity while maintaining high display resolution requirements
2Area of stationary object
If driver circuits are integrated within the display area, then non-display area is reduced and display screen size is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs twin-well CMOS technology with spatially differentiated doping regions (first well area with first-type impurities, second well area with second-type impurities) to create locally optimized transistor characteristics. This allows different regions of the semiconductor substrate to have tailored electrical properties, enabling high-precision circuit operation within the integrated display area while maintaining manufacturability
3Reliability
If twin-well CMOS technology is used with distinct doped regions, then transistor performance and circuit integration are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the semiconductor substrate into distinct first well area and second well area with different doping types. This segmentation allows independent optimization of n-type and p-type transistor regions, improving overall circuit reliability and performance while enabling systematic manufacturing through standardized twin-well CMOS process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively increases the display screen size by minimizing non-display areas, thereby improving user experience and reducing fabrication costs through optimized semiconductor substrate utilization.
Implementation Method 1
the CMOS layer includes a first well area doped with first-type impurities and a second well area doped with second-type impurities
Data Source
AI summary
A display device includes a pixel driver circuit including a plurality of pixel transistors; a scan driver including a first transistor group and a second transistor group; and a display panel including a semiconductor substrate, a complementary metal oxide semiconductor (CMOS) layer on the semiconductor substrate, and an emission material layer on the CMOS layer, wherein the CMOS layer includes a first well area doped with first-type impurities and a second well area doped with second-type impurities, the first and second well areas being in a display area of the display panel, and wherein the plurality of pixel transistors and the first transistor group are in the first well area, and the second transistor group is in the second well area.