Twin-Wire to Single-Wire Bus Interface Conversion
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Solution Overview
Problem
Existing systems face challenges in enabling communication between a twin-wire bus and a single-wire bus, particularly in master-slave configurations where the single-wire bus also supplies power, and in synchronizing data exchanges between such circuits.
Innovation Solution
A method and device for converting a twin-wire bus to a single-wire bus by using a waiting pattern during half-periods of the clock signal, where data bits are set on the clock's rising edge and acknowledgement patterns are converted for transmission, allowing for seamless communication between I2C and single-wire bus protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a twin-wire bus (data and clock) is converted to a single-wire bus for communication, then the number of wires is reduced and compatibility with single-wire protocols is improved, but synchronization of data exchanges between the two circuits becomes problematic
Solution Approach 1:
The patent applies periodic action by using a waiting pattern that occupies the second half-period of each clock cycle. This periodic structure ensures that data bits are transmitted only during the first half-period while the second half-period remains reserved for the waiting pattern, creating a regular rhythm that enables reliable synchronization between twin-wire and single-wire bus protocols without requiring additional synchronization wires.
2Use of energy by moving object
If the single-wire bus is used to also convey power supply, then power consumption is reduced and the bus serves multiple functions, but the communication protocol becomes more complex and reliability decreases
Solution Approach 1:
The patent implements multi-functionality by enabling the single-wire bus to simultaneously convey both data communication and power supply to the slave device. This is achieved by establishing a protocol where the same physical wire carries both functions, reducing the need for separate power wires while maintaining communication reliability through the structured use of clock and data periods.
3Productivity
If data bits are transmitted during both half-periods of the clock signal, then the data transmission speed is doubled, but synchronization and signal interpretation become ambiguous
Solution Approach 1:
The patent applies segmentation by dividing each clock cycle into two distinct half-periods with specific functions: the first half-period is dedicated to data transmission while the second half-period is reserved for the waiting pattern. This temporal segmentation prevents signal ambiguity by ensuring that data bits and waiting patterns occupy separate time intervals, allowing the receiving circuit to reliably interpret signals without confusion while maintaining high transmission efficiency.
Data Source
AI summary
A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period.