Twisted Bit Lines and Differential Sensing for Flash Memory Noise
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Solution Overview
Problem
Flash memory cells can become over-erased, leading to threshold voltage displacement and errors during data reading, as existing methods are either costly or deteriorate read speed without effectively preventing undesirable coupling effects from over-erased cells.
Innovation Solution
The implementation of a memory device with a memory array comprising multiple blocks of bit lines, sense amplifiers, and reference data lines, where the bit lines and reference data lines are strategically allocated and laid out to minimize coupling effects, ensuring balanced capacitance and resistance loading, thereby enhancing reading speed and accuracy by canceling out noise from over-erased cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reading methods are used for flash memory cells, then the reading process is simple, but errors occur due to threshold voltage displacement from over-erased cells
Solution Approach 1:
The bit line is divided into two separate bit lines (first bit line and second bit line), with each connected to a separate input of the sense amplifier. This segmentation allows the sense amplifier to differentially process signals from the two bit lines, canceling out noise from over-erased cells while maintaining reading accuracy.
Solution Approach 2:
A reference cell is introduced as an intermediary element, connected to the second bit line. The reference cell provides a reference signal that helps the sense amplifier distinguish between valid data signals and noise from over-erased cells, thereby improving reading reliability without significantly increasing device complexity.
2Ease of manufacture
If over-erased cells are allowed to operate, then manufacturing cost is reduced, but noise coupling affects reading accuracy
Solution Approach 1:
The invention converts the harmful noise from over-erased cells into a beneficial signal by using differential sensing. The sense amplifier compares signals from two bit lines, and the noise from over-erased cells appears as a common-mode signal that is rejected, thereby allowing over-erased cells to remain operational without degrading reading accuracy.
3Speed
If single bit line configuration is used, then device structure is simple, but reading speed deteriorates due to capacitive loading
Solution Approach 1:
The single bit line is segmented into two separate bit lines, each with its own sense amplifier input. This segmentation reduces the capacitive loading on each individual bit line, allowing faster charging and discharging times, thereby improving reading speed while maintaining a relatively simple device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces errors caused by over-erased cells by canceling out noise in differential sense amplifiers, improving the reliability and speed of data reading in flash memory devices.
Implementation Method 1
a first sense amplifier input is connected to a first bit line and a second sense amplifier input is connected to a second bit line
Data Source
AI summary
Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.