Twisted Bit Line Layout for DRAM Noise and Bonding Alignment
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Solution Overview
Problem
The challenge in manufacturing memory devices with small memory cells, such as 4F2 DRAM cells, is the large array signal noise due to capacitances between bit lines, which can lead to misalignment of contact pads during wafer bonding, resulting in short circuits or open circuits, making it difficult to accurately align and connect twisted bit lines.
Innovation Solution
The solution involves forming a landing pad to correct contact position and using secondary bit lines to connect to sense amplifiers, allowing for proper alignment and bonding of memory cell and CMOS wafers, with twisted bit line architecture to suppress signal noise, and using extra bit lines and word lines to compensate for alignment deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase memory density, then memory capacity increases, but array signal noise increases due to increased capacitances between bit lines
Solution Approach 1:
The bit line is divided into multiple segments (first bit line segment and second bit line segment) that are separated by a first intervening structure. This segmentation reduces the capacitance between adjacent bit lines by increasing the physical separation distance, thereby reducing array signal noise while maintaining high memory density with smaller memory cells
Solution Approach 2:
A first intervening structure is introduced between the first bit line segment and the second bit line segment. This intermediary structure acts as a spacer or isolation element that reduces the capacitive coupling between bit lines, thereby suppressing signal noise without requiring larger memory cell areas
2Object-affected harmful factors
If twisted bit line architecture is used to suppress signal noise, then signal integrity improves, but alignment precision deteriorates during wafer bonding
Solution Approach 1:
Second intervening structures are introduced between the first bit line segment and the second bit line segment at different locations. These intermediary structures serve as alignment references and compensatory features that help maintain precise contact pad alignment during wafer bonding, offsetting the alignment difficulties caused by the twisted bit line configuration
Solution Approach 2:
The twisted bit line structure and intervening structures are designed and positioned in advance during the wafer fabrication process. The alignment features are pre-configured to account for the expected twisting, allowing for preliminary compensation of alignment errors before the actual wafer bonding occurs, thereby ensuring proper alignment precision
3Productivity
If contact pad alignment is made more tolerant to prevent short circuits, then manufacturing yield improves, but electrical connection reliability deteriorates
Solution Approach 1:
Alignment reference structures and compensatory features are built into the bit line architecture in advance. These preliminary alignment aids guide the wafer bonding process to achieve accurate contact pad alignment, ensuring both high manufacturing yield and reliable electrical connections by preventing both short circuits and misalignment errors
Solution Approach 2:
The intervening structures serve dual functions: they reduce signal noise by increasing bit line separation and simultaneously provide alignment reference features that ensure precise contact pad positioning during bonding. This intermediary structure mediates between the need for noise reduction and the need for alignment precision, ensuring both manufacturing yield and electrical connection reliability
Data Source
AI summary
Bit line noise suppression and related apparatuses, methods, and computing systems are disclosed. An apparatus includes a complementary metal-oxide-semiconductor (CMOS) wafer and a memory cell wafer. The CMOS wafer includes CMOS wafer contact pads and sense amplifier circuitry electrically connected to some of the CMOS wafer contact pads. The memory cell wafer includes memory cell wafer contact pads and bit lines electrically connected to some of the memory cell wafer contact pads. The bit lines include primary bit lines and secondary bit lines. Each of the secondary bit lines extends in parallel proximate to a corresponding one of the primary bit lines. A cross intersection of a first primary bit line with a first secondary bit line located proximate to a parity intersection of a second primary bit line with a second secondary bit line. The first primary bit line is adjacent to the second primary bit line.