Twisted Block Select Line Layout for Reliable Non-Volatile Memory
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Solution Overview
Problem
Non-volatile memory devices face challenges in reducing chip size while maintaining reliability due to increased capacitance between metal wirings and semiconductor substrates, affecting program, read, and erase operations.
Innovation Solution
The arrangement of block select lines with twist patterns that change paths in metal lines, reducing coupling capacitance and metal usage, thereby minimizing chip size and preventing unselected block selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block select lines are arranged in conventional straight patterns, then manufacturing is simple, but coupling capacitance between metal wirings increases reducing operational reliability
Solution Approach 1:
The patent applies curvature by introducing twist patterns in the block select lines, transforming them from straight conventional patterns to curved/twisted paths. This curvature changes the spatial relationship between adjacent metal wirings, reducing coupling capacitance and improving operational reliability while maintaining manufacturing feasibility through standard photolithography processes
2Area of stationary object
If chip size is reduced to improve competitiveness, then metal usage decreases, but capacitance between metal wirings and substrate increases reducing reliability
Solution Approach 1:
The patent utilizes the vertical dimension by routing block select lines through multiple layers (first block select lines on a first layer, second block select lines on a second layer) with twist patterns. This three-dimensional arrangement reduces planar metal usage for chip size reduction while managing capacitance effects through spatial separation in the vertical dimension
Solution Approach 2:
The twist patterns introduce curvature to the metal wiring paths, changing the effective geometry to reduce coupling capacitance between adjacent wirings and between wirings and the substrate, thereby maintaining reliability despite reduced chip size
3Reliability
If block select lines are positioned to reduce coupling capacitance, then operational reliability improves, but metal usage increases
Solution Approach 1:
The patent creates a dynamic routing configuration where block select lines can be selectively twisted at different positions along their paths. This allows optimization of capacitance reduction for specific operational requirements while controlling overall metal usage through selective application of twist patterns only where necessary
Data Source
AI summary
According to some embodiments of the inventive concept, there is provided a non-volatile memory device comprising: a memory cell array; a pass transistor circuit electrically connected to the memory cell array; a block select line group including a plurality of block select lines, wherein the plurality of block select lines comprises a first block select line and a second block select line, each of which extends in a first direction on a first layer, and the block select line group is electrically connected to the pass transistor circuit; and a first metal line extending in a second direction on a second layer, wherein the second layer is on the first layer, wherein at least one block select line includes at least one twist pattern that changes a path of the at least one block select line in a hole of the first metal line.