Twisted Digit Line Configurations for Memory Array Noise Reduction
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Solution Overview
Problem
Highly integrated memory arrays face issues with excessive noise due to undesired capacitive coupling between closely spaced digit lines, which becomes more problematic with increasing levels of integration.
Innovation Solution
The implementation of twisted-digit-line-configurations within vertically-stacked memory arrays reduces or eliminates capacitive coupling without the need for shielding, allowing for tighter packing of digit lines and simplifying fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory arrays are highly integrated with closely spaced digit lines, then integration density and productivity are improved, but capacitive coupling between digit lines increases causing excessive noise
Solution Approach 1:
The patent transitions from planar 2D digit line arrangement to a 3D vertically-stacked configuration where digit lines are arranged in multiple decks at different heights. This dimensional change allows digit lines to be closely spaced horizontally for high density while maintaining vertical separation to reduce capacitive coupling noise.
Solution Approach 2:
The patent divides the digit line structure into multiple discrete decks (first deck, second deck, etc.) with digit lines at different vertical levels. Each deck contains specific digit lines (e.g., even-numbered lines in one deck, odd-numbered lines in another), segmenting the originally coupled 2D arrangement into separated 3D segments that reduce interference.
2Object-affected harmful factors
If shielding is added between digit lines to reduce capacitive coupling, then noise is reduced, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent removes the need for shielding structures by extracting the noise reduction function into the spatial arrangement itself. The vertically-stacked deck configuration inherently provides noise reduction through vertical separation, eliminating the requirement for additional shielding layers and simplifying the overall device structure.
3Productivity
If digit lines are tightly packed to increase integration density, then productivity is improved, but capacitive coupling between adjacent digit lines increases
Solution Approach 1:
The patent achieves tight horizontal packing for high density while introducing vertical separation through multi-deck stacking. This allows digit lines to be closely spaced in the horizontal plane for maximum integration density while the vertical dimension provides natural isolation that maintains signal integrity by reducing capacitive coupling.
Solution Approach 2:
The patent creates an asymmetric 3D arrangement where digit lines are positioned at different vertical heights rather than symmetrically in a single plane. This asymmetric stacking pattern (with even and odd lines in different decks) optimizes both density and signal integrity by minimizing parallel coupling distances while maintaining tight packing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces noise between adjacent digit lines during data reading operations, enabling more efficient and densely packed memory array designs.
Implementation Method 1
Problems may be encountered due to undesired capacitive coupling between closely spaced digit lines. The twisted-digit-line-configurations may reduce or eliminate problematic capacitive coupling.
Data Source
AI summary
Some embodiments include an integrated assembly having a first deck, and having a second deck over the first deck. A first true digit line has a first region along the first deck, and has a second region along the second deck. A first complementary digit line has a first region along the first deck, and has a second region along the second deck. The first true digit line is comparatively compared to the first complementary digit line through SENSE AMPLIFIER circuitry. A second digit line has a first region along the first deck and laterally adjacent the first region of the first complementary digit line, and has a second region along the second deck and laterally adjacent the second region of the first true digit line.