Two-Bit Error Correction Circuit With Reduced Root Lookup Tables
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Solution Overview
Problem
Conventional two-bit error correction methods using block error correcting codes require large tables for table lookup, leading to increased circuit scale due to the size of the tables needed for root calculation.
Innovation Solution
The error correction apparatus employs a syndrome generation unit, number-of-errors determination unit, and a two-bit error candidate error correction unit to calculate a normalized parameter, except uncorrectable errors, and obtain a normalized root using a degeneracy parameter, reducing the size of required tables through normalization and degeneracy processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If table lookup is used for root calculation in two-bit error correction, then error correction capability is achieved, but circuit scale increases due to large table size
Solution Approach 1:
The patent segments the root calculation process into two parts: (1) calculate a preliminary parameter P from syndrome values, and (2) use P to index into a reduced-size table to obtain the root. This segmentation allows the table to be much smaller than a direct syndrome-to-root table, reducing circuit scale while maintaining error correction capability.
Solution Approach 2:
The patent introduces an intermediate parameter P that is derived from the syndrome values through a specific calculation (P = S3/S1 + 1). This parameter transformation changes the indexing key from the full syndrome pattern to a compressed representation, enabling the use of a smaller lookup table while preserving the ability to correctly identify error locations.
2Reliability
If normalized parameter table is used for root calculation, then error correction is performed, but the table size remains large for high-rate codes
Solution Approach 1:
The patent applies parameter transformation by calculating P = S3/S1 + 1 from the syndrome values. This parameter change compresses the information needed for root calculation into a smaller representation, reducing the table size from requiring all possible syndrome patterns to only requiring entries indexed by the compressed parameter P.
Solution Approach 2:
The patent creates a compressed copy of the essential error location information through the parameter P, which captures the necessary relationships between syndrome values and error locations without storing the full syndrome-to-root mapping. This copying approach reduces table size while maintaining correction capability.
Data Source
AI summary
An error correction apparatus that performs two-bit error correction decoding using a block error correcting code includes: a syndrome generation unit that generates a syndrome pattern from a reception sequence; a number-of-errors determination unit that determines a number of bit errors in the reception sequence based on the syndrome pattern; and a two-bit error candidate error correction unit that calculates a first parameter based on the syndrome pattern when the number-of-errors determination unit determines that there is a two-bit error with a possibility of correction thereof, excepts the first parameter when the two-bit error is uncorrectable, and obtains a normalized root for the two-bit error by using a second parameter obtained by degeneracy of the first parameter by one bit, the first parameter being a constant term of a normalized polynomial, the normalized polynomial being obtained by normalization of a quadratic error locator polynomial.